mem-cache: Support for page crossing prefetches

Prefetchers can now issue hardware prefetch requests that go beyond
the boundaries of the system page. Page crossing references will need
to look up the TLBs to be able to compute the physical address to be
prefetched.

Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14620
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

1 files changed, 12 insertions, 0 deletions

diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index f4a61b21a..e31dbfd40 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -52,6 +52,7 @@
 #include <cstdint>
 
 #include "arch/isa_traits.hh"
+#include "arch/generic/tlb.hh"
 #include "base/statistics.hh"
 #include "base/types.hh"
 #include "mem/packet.hh"
@@ -326,6 +327,9 @@ class BasePrefetcher : public ClockedObject
     /** Total prefetches that has been useful */
     uint64_t usefulPrefetches;
 
+    /** Registered tlb for address translations */
+    BaseTLB * tlb;
+
   public:
 
     BasePrefetcher(const BasePrefetcherParams *p);
@@ -371,5 +375,13 @@ class BasePrefetcher : public ClockedObject
      * @param name The probe name
      */
     void addEventProbe(SimObject *obj, const char *name);
+
+    /**
+     * Add a BaseTLB object to be used whenever a translation is needed.
+     * This is generally required when the prefetcher is allowed to generate
+     * page crossing references and/or uses virtual addresses for training.
+     * @param tlb pointer to the BaseTLB object to add
+     */
+    void addTLB(BaseTLB *tlb);
 };
 #endif //__MEM_CACHE_PREFETCH_BASE_HH__