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author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-17 17:30:24 -0700 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-17 17:30:24 -0700 |
commit | d69a763833f911cb2d7f97604108219b4da0b881 (patch) | |
tree | 538d12c555824c931a3ceaedea5a2f46aa4e5212 /src/mem/cache/prefetch/base_prefetcher.cc | |
parent | c2a97387cf543061bdb02f5259875b10a4dd6f74 (diff) | |
parent | 35cf19d441ed15d054d00674ec67ab5bc769f6d7 (diff) | |
download | gem5-d69a763833f911cb2d7f97604108219b4da0b881.tar.xz |
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
configs/example/memtest.py:
Hand merge redundant changes.
--HG--
extra : convert_revision : a2e36be254bf052024f37bcb23b5209f367d37e1
Diffstat (limited to 'src/mem/cache/prefetch/base_prefetcher.cc')
-rw-r--r-- | src/mem/cache/prefetch/base_prefetcher.cc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/mem/cache/prefetch/base_prefetcher.cc b/src/mem/cache/prefetch/base_prefetcher.cc index 44daf75e1..d03cfe3ae 100644 --- a/src/mem/cache/prefetch/base_prefetcher.cc +++ b/src/mem/cache/prefetch/base_prefetcher.cc @@ -141,7 +141,7 @@ BasePrefetcher::getPacket() keepTrying = cache->inCache(pkt->getAddr()); } if (pf.empty()) { - cache->clearMasterRequest(Request_PF); + cache->deassertMemSideBusRequest(Request_PF); if (keepTrying) return NULL; //None left, all were in cache } } while (keepTrying); @@ -165,7 +165,7 @@ BasePrefetcher::handleMiss(PacketPtr &pkt, Tick time) pfRemovedMSHR++; pf.erase(iter); if (pf.empty()) - cache->clearMasterRequest(Request_PF); + cache->deassertMemSideBusRequest(Request_PF); } //Remove anything in queue with delay older than time @@ -182,7 +182,7 @@ BasePrefetcher::handleMiss(PacketPtr &pkt, Tick time) iter--; } if (pf.empty()) - cache->clearMasterRequest(Request_PF); + cache->deassertMemSideBusRequest(Request_PF); } @@ -241,10 +241,9 @@ BasePrefetcher::handleMiss(PacketPtr &pkt, Tick time) } pf.push_back(prefetch); - prefetch->flags |= CACHE_LINE_FILL; //Make sure to request the bus, with proper delay - cache->setMasterRequest(Request_PF, prefetch->time); + cache->requestMemSideBus(Request_PF, prefetch->time); //Increment through the list addr++; |