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author | Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> | 2012-02-12 16:07:38 -0600 |
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committer | Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> | 2012-02-12 16:07:38 -0600 |
commit | 7e104a1af235823e3d641a972ea920937f7ec67d (patch) | |
tree | d109d98f09652ed11b08dfe0d93a531b28d14df7 /src/mem/cache/prefetch/ghb.hh | |
parent | b7cf64398f16e93f118060bd49313f1d37f0e324 (diff) | |
download | gem5-7e104a1af235823e3d641a972ea920937f7ec67d.tar.xz |
prefetcher: Make prefetcher a sim object instead of it being a parameter on cache
Diffstat (limited to 'src/mem/cache/prefetch/ghb.hh')
-rw-r--r-- | src/mem/cache/prefetch/ghb.hh | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/src/mem/cache/prefetch/ghb.hh b/src/mem/cache/prefetch/ghb.hh index c85221a39..a21b57b93 100644 --- a/src/mem/cache/prefetch/ghb.hh +++ b/src/mem/cache/prefetch/ghb.hh @@ -37,6 +37,7 @@ #define __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__ #include "mem/cache/prefetch/base.hh" +#include "params/GHBPrefetcher.hh" class GHBPrefetcher : public BasePrefetcher { @@ -47,15 +48,9 @@ class GHBPrefetcher : public BasePrefetcher Addr secondLastMissAddr[Max_Contexts]; Addr lastMissAddr[Max_Contexts]; - Tick latency; - int degree; - bool useContextId; - public: - - GHBPrefetcher(const BaseCacheParams *p) - : BasePrefetcher(p), latency(p->prefetch_latency), - degree(p->prefetch_degree), useContextId(p->prefetch_use_cpu_id) + GHBPrefetcher(const Params *p) + : BasePrefetcher(p) { } |