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authorAndreas Hansson <andreas.hansson@arm.com>2015-07-30 03:41:43 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-07-30 03:41:43 -0400
commit540e59fd7088fef6cc564babf8c728487b82afd5 (patch)
treece90cac12b6b8087fc5480851138dba13e26e655 /src/mem/cache/prefetch/queued.cc
parent0c89c15b23d4db50eb08f8ebf2a40b569f41dd29 (diff)
downloadgem5-540e59fd7088fef6cc564babf8c728487b82afd5.tar.xz
mem: Remove unused RequestCause in cache
This patch removes the RequestCause, and also simplifies how we schedule the sending of packets through the memory-side port. The deassertion of bus requests is removed as it is not used.
Diffstat (limited to 'src/mem/cache/prefetch/queued.cc')
-rw-r--r--src/mem/cache/prefetch/queued.cc3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mem/cache/prefetch/queued.cc b/src/mem/cache/prefetch/queued.cc
index 58b33a4ae..03ca3188f 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -79,9 +79,6 @@ QueuedPrefetcher::notify(const PacketPtr &pkt)
++itr;
}
}
-
- if (pfq.empty())
- cache->deassertMemSideBusRequest(BaseCache::Request_PF);
}
// Calculate prefetches given this access