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author | Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E) <mitch.hayenga+gem5@gmail.com> | 2014-01-29 23:21:25 -0600 |
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committer | Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E) <mitch.hayenga+gem5@gmail.com> | 2014-01-29 23:21:25 -0600 |
commit | 95735e10e7ea85320ee39c15a4132eece8417af4 (patch) | |
tree | 370863ea1bb2413937c03218e0b59aecc7a76fbe /src/mem/cache/prefetch/stride.cc | |
parent | 32cc2ea8b9173863adeaa03f4d7ee1635acfdef7 (diff) | |
download | gem5-95735e10e7ea85320ee39c15a4132eece8417af4.tar.xz |
mem: prefetcher: add options, support for unaligned addresses
This patch extends the classic prefetcher to work on non-block aligned
addresses. Because the existing prefetchers in gem5 mask off the lower
address bits of cache accesses, many predictable strides fail to be
detected. For example, if a load were to stride by 48 bytes, with 64 byte
cachelines, the current stride based prefetcher would see an access pattern
of 0, 64, 64, 128, 192.... Thus not detecting a constant stride pattern. This
patch fixes this, by training the prefetcher on access and not masking off the
lower address bits.
It also adds the following configuration options:
1) Training/prefetching only on cache misses,
2) Training/prefetching only on data acceses,
3) Optionally tagging prefetches with a PC address.
#3 allows prefetchers to train off of prefetch requests in systems with
multiple cache levels and PC-based prefetchers present at multiple levels.
It also effectively allows a pipelining of prefetch requests (like in POWER4)
across multiple levels of cache hierarchy.
Improves performance on my gem5 configuration by 4.3% for SPECINT and 4.7% for SPECFP (geomean).
Diffstat (limited to 'src/mem/cache/prefetch/stride.cc')
-rw-r--r-- | src/mem/cache/prefetch/stride.cc | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/mem/cache/prefetch/stride.cc b/src/mem/cache/prefetch/stride.cc index fd8b20fcc..a7abf4809 100644 --- a/src/mem/cache/prefetch/stride.cc +++ b/src/mem/cache/prefetch/stride.cc @@ -59,7 +59,7 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, return; } - Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); + Addr data_addr = pkt->getAddr(); bool is_secure = pkt->isSecure(); MasterID master_id = useMasterId ? pkt->req->masterId() : 0; Addr pc = pkt->req->getPC(); @@ -77,7 +77,7 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, if (iter != tab.end()) { // Hit in table - int new_stride = blk_addr - (*iter)->missAddr; + int new_stride = data_addr - (*iter)->missAddr; bool stride_match = (new_stride == (*iter)->stride); if (stride_match && new_stride != 0) { @@ -89,20 +89,20 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, (*iter)->confidence = 0; } - DPRINTF(HWPrefetch, "hit: PC %x blk_addr %x (%s) stride %d (%s), " - "conf %d\n", pc, blk_addr, is_secure ? "s" : "ns", new_stride, + DPRINTF(HWPrefetch, "hit: PC %x data_addr %x (%s) stride %d (%s), " + "conf %d\n", pc, data_addr, is_secure ? "s" : "ns", new_stride, stride_match ? "match" : "change", (*iter)->confidence); - (*iter)->missAddr = blk_addr; + (*iter)->missAddr = data_addr; (*iter)->isSecure = is_secure; if ((*iter)->confidence <= 0) return; for (int d = 1; d <= degree; d++) { - Addr new_addr = blk_addr + d * new_stride; - if (pageStop && !samePage(blk_addr, new_addr)) { + Addr new_addr = data_addr + d * new_stride; + if (pageStop && !samePage(data_addr, new_addr)) { // Spanned the page, so now stop pfSpanPage += degree - d + 1; return; @@ -117,7 +117,7 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, // Miss in table // Find lowest confidence and replace - DPRINTF(HWPrefetch, "miss: PC %x blk_addr %x (%s)\n", pc, blk_addr, + DPRINTF(HWPrefetch, "miss: PC %x data_addr %x (%s)\n", pc, data_addr, is_secure ? "s" : "ns"); if (tab.size() >= 256) { //set default table size is 256 @@ -139,7 +139,7 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, StrideEntry *new_entry = new StrideEntry; new_entry->instAddr = pc; - new_entry->missAddr = blk_addr; + new_entry->missAddr = data_addr; new_entry->isSecure = is_secure; new_entry->stride = 0; new_entry->confidence = 0; |