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author | Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> | 2012-02-12 16:07:38 -0600 |
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committer | Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> | 2012-02-12 16:07:38 -0600 |
commit | 7e104a1af235823e3d641a972ea920937f7ec67d (patch) | |
tree | d109d98f09652ed11b08dfe0d93a531b28d14df7 /src/mem/cache/prefetch/stride.hh | |
parent | b7cf64398f16e93f118060bd49313f1d37f0e324 (diff) | |
download | gem5-7e104a1af235823e3d641a972ea920937f7ec67d.tar.xz |
prefetcher: Make prefetcher a sim object instead of it being a parameter on cache
Diffstat (limited to 'src/mem/cache/prefetch/stride.hh')
-rw-r--r-- | src/mem/cache/prefetch/stride.hh | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/mem/cache/prefetch/stride.hh b/src/mem/cache/prefetch/stride.hh index c78739b4e..51b4252a1 100644 --- a/src/mem/cache/prefetch/stride.hh +++ b/src/mem/cache/prefetch/stride.hh @@ -39,6 +39,7 @@ #include <climits> #include "mem/cache/prefetch/base.hh" +#include "params/StridePrefetcher.hh" class StridePrefetcher : public BasePrefetcher { @@ -63,15 +64,11 @@ class StridePrefetcher : public BasePrefetcher Addr *lastMissAddr[Max_Contexts]; std::list<StrideEntry*> table[Max_Contexts]; - Tick latency; - int degree; - bool useContextId; public: - StridePrefetcher(const BaseCacheParams *p) - : BasePrefetcher(p), latency(p->prefetch_latency), - degree(p->prefetch_degree), useContextId(p->prefetch_use_cpu_id) + StridePrefetcher(const Params *p) + : BasePrefetcher(p) { } |