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author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-04 09:10:53 -0800 |
---|---|---|
committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-04 09:10:53 -0800 |
commit | 5fbf3aa47112b3d28971c0bab604ce9cc3f67b16 (patch) | |
tree | f38e2827f802c205d8373d68d125a8d17aa5e4ee /src/mem/cache/prefetch | |
parent | 51e3688701fe66987f96c5ddc5b8f111f4ad94d6 (diff) | |
download | gem5-5fbf3aa47112b3d28971c0bab604ce9cc3f67b16.tar.xz |
Turn cache MissQueue/BlockingBuffer into virtual object
instead of template parameter.
--HG--
extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0
Diffstat (limited to 'src/mem/cache/prefetch')
-rw-r--r-- | src/mem/cache/prefetch/ghb_prefetcher.cc | 6 | ||||
-rw-r--r-- | src/mem/cache/prefetch/ghb_prefetcher.hh | 10 | ||||
-rw-r--r-- | src/mem/cache/prefetch/stride_prefetcher.cc | 6 | ||||
-rw-r--r-- | src/mem/cache/prefetch/stride_prefetcher.hh | 10 | ||||
-rw-r--r-- | src/mem/cache/prefetch/tagged_prefetcher.hh | 8 | ||||
-rw-r--r-- | src/mem/cache/prefetch/tagged_prefetcher_impl.hh | 10 |
6 files changed, 21 insertions, 29 deletions
diff --git a/src/mem/cache/prefetch/ghb_prefetcher.cc b/src/mem/cache/prefetch/ghb_prefetcher.cc index dd1b8aee4..a6c419113 100644 --- a/src/mem/cache/prefetch/ghb_prefetcher.cc +++ b/src/mem/cache/prefetch/ghb_prefetcher.cc @@ -38,15 +38,11 @@ #include "mem/cache/tags/lru.hh" -#include "mem/cache/miss/miss_queue.hh" -#include "mem/cache/miss/blocking_buffer.hh" - #include "mem/cache/prefetch/ghb_prefetcher.hh" // Template Instantiations #ifndef DOXYGEN_SHOULD_SKIP_THIS -template class GHBPrefetcher<CacheTags<LRU>, MissQueue>; -template class GHBPrefetcher<CacheTags<LRU>, BlockingBuffer>; +template class GHBPrefetcher<CacheTags<LRU> >; #endif //DOXYGEN_SHOULD_SKIP_THIS diff --git a/src/mem/cache/prefetch/ghb_prefetcher.hh b/src/mem/cache/prefetch/ghb_prefetcher.hh index 14f5747df..c558a3e64 100644 --- a/src/mem/cache/prefetch/ghb_prefetcher.hh +++ b/src/mem/cache/prefetch/ghb_prefetcher.hh @@ -43,16 +43,16 @@ /** * A template-policy based cache. The behavior of the cache can be altered by * supplying different template policies. TagStore handles all tag and data - * storage @sa TagStore. Buffering handles all misses and writes/writebacks + * storage @sa TagStore. MissBuffer handles all misses and writes/writebacks * @sa MissQueue. Coherence handles all coherence policy details @sa * UniCoherence, SimpleMultiCoherence. */ -template <class TagStore, class Buffering> -class GHBPrefetcher : public Prefetcher<TagStore, Buffering> +template <class TagStore> +class GHBPrefetcher : public Prefetcher<TagStore> { protected: - Buffering* mq; + MissBuffer* mq; TagStore* tags; Addr second_last_miss_addr[64/*MAX_CPUS*/]; @@ -67,7 +67,7 @@ class GHBPrefetcher : public Prefetcher<TagStore, Buffering> GHBPrefetcher(int size, bool pageStop, bool serialSquash, bool cacheCheckPush, bool onlyData, Tick latency, int degree, bool useCPUId) - :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash, + :Prefetcher<TagStore>(size, pageStop, serialSquash, cacheCheckPush, onlyData), latency(latency), degree(degree), useCPUId(useCPUId) { diff --git a/src/mem/cache/prefetch/stride_prefetcher.cc b/src/mem/cache/prefetch/stride_prefetcher.cc index c3b428dab..2204871cc 100644 --- a/src/mem/cache/prefetch/stride_prefetcher.cc +++ b/src/mem/cache/prefetch/stride_prefetcher.cc @@ -38,15 +38,11 @@ #include "mem/cache/tags/lru.hh" -#include "mem/cache/miss/miss_queue.hh" -#include "mem/cache/miss/blocking_buffer.hh" - #include "mem/cache/prefetch/stride_prefetcher.hh" // Template Instantiations #ifndef DOXYGEN_SHOULD_SKIP_THIS -template class StridePrefetcher<CacheTags<LRU>, MissQueue>; -template class StridePrefetcher<CacheTags<LRU>, BlockingBuffer>; +template class StridePrefetcher<CacheTags<LRU> >; #endif //DOXYGEN_SHOULD_SKIP_THIS diff --git a/src/mem/cache/prefetch/stride_prefetcher.hh b/src/mem/cache/prefetch/stride_prefetcher.hh index d6fb8ab66..57e430400 100644 --- a/src/mem/cache/prefetch/stride_prefetcher.hh +++ b/src/mem/cache/prefetch/stride_prefetcher.hh @@ -43,16 +43,16 @@ /** * A template-policy based cache. The behavior of the cache can be altered by * supplying different template policies. TagStore handles all tag and data - * storage @sa TagStore. Buffering handles all misses and writes/writebacks + * storage @sa TagStore. MissBuffer handles all misses and writes/writebacks * @sa MissQueue. Coherence handles all coherence policy details @sa * UniCoherence, SimpleMultiCoherence. */ -template <class TagStore, class Buffering> -class StridePrefetcher : public Prefetcher<TagStore, Buffering> +template <class TagStore> +class StridePrefetcher : public Prefetcher<TagStore> { protected: - Buffering* mq; + MissBuffer* mq; TagStore* tags; class strideEntry @@ -84,7 +84,7 @@ class StridePrefetcher : public Prefetcher<TagStore, Buffering> StridePrefetcher(int size, bool pageStop, bool serialSquash, bool cacheCheckPush, bool onlyData, Tick latency, int degree, bool useCPUId) - :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash, + :Prefetcher<TagStore>(size, pageStop, serialSquash, cacheCheckPush, onlyData), latency(latency), degree(degree), useCPUId(useCPUId) { diff --git a/src/mem/cache/prefetch/tagged_prefetcher.hh b/src/mem/cache/prefetch/tagged_prefetcher.hh index b61e57dcc..dc2aaec50 100644 --- a/src/mem/cache/prefetch/tagged_prefetcher.hh +++ b/src/mem/cache/prefetch/tagged_prefetcher.hh @@ -41,16 +41,16 @@ /** * A template-policy based cache. The behavior of the cache can be altered by * supplying different template policies. TagStore handles all tag and data - * storage @sa TagStore. Buffering handles all misses and writes/writebacks + * storage @sa TagStore. MissBuffer handles all misses and writes/writebacks * @sa MissQueue. Coherence handles all coherence policy details @sa * UniCoherence, SimpleMultiCoherence. */ -template <class TagStore, class Buffering> -class TaggedPrefetcher : public Prefetcher<TagStore, Buffering> +template <class TagStore> +class TaggedPrefetcher : public Prefetcher<TagStore> { protected: - Buffering* mq; + MissBuffer* mq; TagStore* tags; Tick latency; diff --git a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh index a18de4571..b3d4284c7 100644 --- a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh +++ b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh @@ -36,20 +36,20 @@ #include "arch/isa_traits.hh" #include "mem/cache/prefetch/tagged_prefetcher.hh" -template <class TagStore, class Buffering> -TaggedPrefetcher<TagStore, Buffering>:: +template <class TagStore> +TaggedPrefetcher<TagStore>:: TaggedPrefetcher(int size, bool pageStop, bool serialSquash, bool cacheCheckPush, bool onlyData, Tick latency, int degree) - :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash, + :Prefetcher<TagStore>(size, pageStop, serialSquash, cacheCheckPush, onlyData), latency(latency), degree(degree) { } -template <class TagStore, class Buffering> +template <class TagStore> void -TaggedPrefetcher<TagStore, Buffering>:: +TaggedPrefetcher<TagStore>:: calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, std::list<Tick> &delays) { |