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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-06-28 14:35:00 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-06-28 14:35:00 -0400 |
commit | fc281d0b64fca8d2809ec462148acb7cf0461ea5 (patch) | |
tree | ef772f136f4e1bad0e9de6282201aa6611329fc7 /src/mem/cache/prefetch | |
parent | ed8564a6b9f0702a40995d95cc4da54de3d35462 (diff) | |
download | gem5-fc281d0b64fca8d2809ec462148acb7cf0461ea5.tar.xz |
Backing in more changsets, getting closer to compile
base_cache.cc compiles, continuing on
src/SConscript:
Add in compilation flags for cache files
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
Back in more fixes, now base_cache compiles
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lru.cc:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/request.hh:
Backing in more changsets, getting closer to compile
--HG--
extra : convert_revision : ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed
Diffstat (limited to 'src/mem/cache/prefetch')
-rw-r--r-- | src/mem/cache/prefetch/base_prefetcher.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/prefetch/base_prefetcher.cc b/src/mem/cache/prefetch/base_prefetcher.cc index 14beef260..7b2d57cd5 100644 --- a/src/mem/cache/prefetch/base_prefetcher.cc +++ b/src/mem/cache/prefetch/base_prefetcher.cc @@ -132,7 +132,7 @@ BasePrefetcher::getPacket() void BasePrefetcher::handleMiss(Packet * &pkt, Tick time) { - if (!pkt->isUncacheable() && !(pkt->isInstRead() && only_data)) + if (!pkt->req->isUncacheable() && !(pkt->isInstRead() && only_data)) { //Calculate the blk address Addr blkAddr = pkt->paddr & ~(Addr)(blkSize-1); @@ -185,7 +185,7 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time) prefetch->xc = pkt->xc; prefetch->data = new uint8_t[blkSize]; prefetch->req->asid = pkt->req->asid; - prefetch->thread_num = pkt->thread_num; + prefetch->req->setThreadNum() = pkt->req->getThreadNum(); prefetch->time = time + (*delay); //@todo ADD LATENCY HERE //... initialize |