mem: Add support for a security bit in the memory system

This patch adds the basic building blocks required to support e.g. ARM
TrustZone by discerning secure and non-secure memory accesses.

6 files changed, 100 insertions, 25 deletions

diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index ed7b63f82..c440978e6 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -122,9 +122,9 @@ BasePrefetcher::regStats()
 }
 
 inline bool
-BasePrefetcher::inCache(Addr addr)
+BasePrefetcher::inCache(Addr addr, bool is_secure)
 {
-    if (cache->inCache(addr)) {
+    if (cache->inCache(addr, is_secure)) {
         pfCacheHit++;
         return true;
     }
@@ -132,9 +132,9 @@ BasePrefetcher::inCache(Addr addr)
 }
 
 inline bool
-BasePrefetcher::inMissQueue(Addr addr)
+BasePrefetcher::inMissQueue(Addr addr, bool is_secure)
 {
-    if (cache->inMissQueue(addr)) {
+    if (cache->inMissQueue(addr, is_secure)) {
         pfMSHRHit++;
         return true;
     }
@@ -157,12 +157,14 @@ BasePrefetcher::getPacket()
         pf.pop_front();
 
         Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
+        bool is_secure = pkt->isSecure();
 
-        if (!inCache(blk_addr) && !inMissQueue(blk_addr))
+        if (!inCache(blk_addr, is_secure) && !inMissQueue(blk_addr, is_secure))
             // we found a prefetch, return it
             break;
 
-        DPRINTF(HWPrefetch, "addr 0x%x in cache, skipping\n", pkt->getAddr());
+        DPRINTF(HWPrefetch, "addr 0x%x (%s) in cache, skipping\n",
+                pkt->getAddr(), is_secure ? "s" : "ns");
         delete pkt->req;
         delete pkt;
 
@@ -174,7 +176,8 @@ BasePrefetcher::getPacket()
 
     pfIssued++;
     assert(pkt != NULL);
-    DPRINTF(HWPrefetch, "returning 0x%x\n", pkt->getAddr());
+    DPRINTF(HWPrefetch, "returning 0x%x (%s)\n", pkt->getAddr(),
+            pkt->isSecure() ? "s" : "ns");
     return pkt;
 }
 
@@ -185,12 +188,15 @@ BasePrefetcher::notify(PacketPtr &pkt, Tick tick)
     if (!pkt->req->isUncacheable() && !(pkt->req->isInstFetch() && onlyData)) {
         // Calculate the blk address
         Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
+        bool is_secure = pkt->isSecure();
 
         // Check if miss is in pfq, if so remove it
-        std::list<DeferredPacket>::iterator iter = inPrefetch(blk_addr);
+        std::list<DeferredPacket>::iterator iter = inPrefetch(blk_addr,
+                                                              is_secure);
         if (iter != pf.end()) {
             DPRINTF(HWPrefetch, "Saw a miss to a queued prefetch addr: "
-                    "0x%x, removing it\n", blk_addr);
+                    "0x%x (%s), removing it\n", blk_addr,
+                    is_secure ? "s" : "ns");
             pfRemovedMSHR++;
             delete iter->pkt->req;
             delete iter->pkt;
@@ -239,7 +245,7 @@ BasePrefetcher::notify(PacketPtr &pkt, Tick tick)
                     addr, *delayIter, time);
 
             // Check if it is already in the pf buffer
-            if (inPrefetch(addr) != pf.end()) {
+            if (inPrefetch(addr, is_secure) != pf.end()) {
                 pfBufferHit++;
                 DPRINTF(HWPrefetch, "Prefetch addr already in pf buffer\n");
                 continue;
@@ -247,6 +253,8 @@ BasePrefetcher::notify(PacketPtr &pkt, Tick tick)
 
             // create a prefetch memreq
             Request *prefetchReq = new Request(*addrIter, blkSize, 0, masterId);
+            if (is_secure)
+                prefetchReq->setFlags(Request::SECURE);
             prefetchReq->taskId(ContextSwitchTaskId::Prefetcher);
             PacketPtr prefetch =
                 new Packet(prefetchReq, MemCmd::HardPFReq);
@@ -274,12 +282,13 @@ BasePrefetcher::notify(PacketPtr &pkt, Tick tick)
 }
 
 std::list<BasePrefetcher::DeferredPacket>::iterator
-BasePrefetcher::inPrefetch(Addr address)
+BasePrefetcher::inPrefetch(Addr address, bool is_secure)
 {
     // Guaranteed to only be one match, we always check before inserting
     std::list<DeferredPacket>::iterator iter;
     for (iter = pf.begin(); iter != pf.end(); iter++) {
-        if ((iter->pkt->getAddr() & ~(Addr)(blkSize-1)) == address) {
+        if (((*iter).pkt->getAddr() & ~(Addr)(blkSize-1)) == address &&
+            (*iter).pkt->isSecure() == is_secure) {
             return iter;
         }
     }
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 07ca3dd6f..953852c38 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -137,9 +137,9 @@ class BasePrefetcher : public ClockedObject
      */
     Tick notify(PacketPtr &pkt, Tick tick);
 
-    bool inCache(Addr addr);
+    bool inCache(Addr addr, bool is_secure);
 
-    bool inMissQueue(Addr addr);
+    bool inMissQueue(Addr addr, bool is_secure);
 
     PacketPtr getPacket();
 
@@ -157,7 +157,7 @@ class BasePrefetcher : public ClockedObject
                                    std::list<Addr> &addresses,
                                    std::list<Cycles> &delays) = 0;
 
-    std::list<DeferredPacket>::iterator inPrefetch(Addr address);
+    std::list<DeferredPacket>::iterator inPrefetch(Addr address, bool is_secure);
 
     /**
      * Utility function: are addresses a and b on the same VM page?
diff --git a/src/mem/cache/prefetch/ghb.cc b/src/mem/cache/prefetch/ghb.cc
index 9ceb051a7..e153c777d 100644
--- a/src/mem/cache/prefetch/ghb.cc
+++ b/src/mem/cache/prefetch/ghb.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012-2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -43,16 +55,26 @@ GHBPrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
                                  std::list<Cycles> &delays)
 {
     Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
+    bool is_secure = pkt->isSecure();
     int master_id = useMasterId ? pkt->req->masterId() : 0;
     assert(master_id < Max_Masters);
 
+    bool same_sec_state = true;
+    // Avoid activating prefetch if the security state is not
+    // consistent across requests
+    if (is_secure != lastMissIsSecure[master_id] ||
+        is_secure != secondLastMissIsSecure[master_id])
+        same_sec_state = false;
+
     int new_stride = blk_addr - lastMissAddr[master_id];
     int old_stride = lastMissAddr[master_id] - secondLastMissAddr[master_id];
 
     secondLastMissAddr[master_id] = lastMissAddr[master_id];
+    secondLastMissIsSecure[master_id] = lastMissIsSecure[master_id];
     lastMissAddr[master_id] = blk_addr;
+    lastMissIsSecure[master_id] = is_secure;
 
-    if (new_stride == old_stride) {
+    if (same_sec_state && new_stride == old_stride) {
         for (int d = 1; d <= degree; d++) {
             Addr new_addr = blk_addr + d * new_stride;
             if (pageStop && !samePage(blk_addr, new_addr)) {
diff --git a/src/mem/cache/prefetch/ghb.hh b/src/mem/cache/prefetch/ghb.hh
index 3e4123de0..9ddff1160 100644
--- a/src/mem/cache/prefetch/ghb.hh
+++ b/src/mem/cache/prefetch/ghb.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012-2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -46,7 +58,9 @@ class GHBPrefetcher : public BasePrefetcher
     static const int Max_Masters = 64;
 
     Addr secondLastMissAddr[Max_Masters];
+    bool secondLastMissIsSecure[Max_Masters];
     Addr lastMissAddr[Max_Masters];
+    bool lastMissIsSecure[Max_Masters];
 
   public:
     GHBPrefetcher(const Params *p)
diff --git a/src/mem/cache/prefetch/stride.cc b/src/mem/cache/prefetch/stride.cc
index cb67f50f8..fd8b20fcc 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012-2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -48,6 +60,7 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
     }
 
     Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
+    bool is_secure = pkt->isSecure();
     MasterID master_id = useMasterId ? pkt->req->masterId() : 0;
     Addr pc = pkt->req->getPC();
     assert(master_id < Max_Contexts);
@@ -56,7 +69,8 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
     /* Scan Table for instAddr Match */
     std::list<StrideEntry*>::iterator iter;
     for (iter = tab.begin(); iter != tab.end(); iter++) {
-        if ((*iter)->instAddr == pc)
+        // Entries have to match on the security state as well
+        if ((*iter)->instAddr == pc && (*iter)->isSecure == is_secure)
             break;
     }
 
@@ -75,11 +89,13 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
                 (*iter)->confidence = 0;
         }
 
-        DPRINTF(HWPrefetch, "hit: PC %x blk_addr %x stride %d (%s), conf %d\n",
-                pc, blk_addr, new_stride, stride_match ? "match" : "change",
+        DPRINTF(HWPrefetch, "hit: PC %x blk_addr %x (%s) stride %d (%s), "
+                "conf %d\n", pc, blk_addr, is_secure ? "s" : "ns", new_stride,
+                stride_match ? "match" : "change",
                 (*iter)->confidence);
 
         (*iter)->missAddr = blk_addr;
+        (*iter)->isSecure = is_secure;
 
         if ((*iter)->confidence <= 0)
             return;
@@ -91,8 +107,8 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
                 pfSpanPage += degree - d + 1;
                 return;
             } else {
-                DPRINTF(HWPrefetch, "  queuing prefetch to %x @ %d\n",
-                        new_addr, latency);
+                DPRINTF(HWPrefetch, "  queuing prefetch to %x (%s) @ %d\n",
+                        new_addr, is_secure ? "s" : "ns", latency);
                 addresses.push_back(new_addr);
                 delays.push_back(latency);
             }
@@ -101,7 +117,8 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
         // Miss in table
         // Find lowest confidence and replace
 
-        DPRINTF(HWPrefetch, "miss: PC %x blk_addr %x\n", pc, blk_addr);
+        DPRINTF(HWPrefetch, "miss: PC %x blk_addr %x (%s)\n", pc, blk_addr,
+                is_secure ? "s" : "ns");
 
         if (tab.size() >= 256) { //set default table size is 256
             std::list<StrideEntry*>::iterator min_pos = tab.begin();
@@ -112,7 +129,8 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
                     min_conf = (*iter)->confidence;
                 }
             }
-            DPRINTF(HWPrefetch, "  replacing PC %x\n", (*min_pos)->instAddr);
+            DPRINTF(HWPrefetch, "  replacing PC %x (%s)\n",
+                    (*min_pos)->instAddr, (*min_pos)->isSecure ? "s" : "ns");
 
             // free entry and delete it
             delete *min_pos;
@@ -122,6 +140,7 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
         StrideEntry *new_entry = new StrideEntry;
         new_entry->instAddr = pc;
         new_entry->missAddr = blk_addr;
+        new_entry->isSecure = is_secure;
         new_entry->stride = 0;
         new_entry->confidence = 0;
         tab.push_back(new_entry);
diff --git a/src/mem/cache/prefetch/stride.hh b/src/mem/cache/prefetch/stride.hh
index 89ac7acad..b02d97d56 100644
--- a/src/mem/cache/prefetch/stride.hh
+++ b/src/mem/cache/prefetch/stride.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012-2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -57,12 +69,11 @@ class StridePrefetcher : public BasePrefetcher
       public:
         Addr instAddr;
         Addr missAddr;
+        bool isSecure;
         int stride;
         int confidence;
     };
 
-    Addr *lastMissAddr[Max_Contexts];
-
     std::list<StrideEntry*> table[Max_Contexts];
 
   public: