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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-02-05 09:45:20 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-05-31 17:45:23 +0000 |
| commit | 51056cec69a72931a319e7be9370ea63f18e1aa3 (patch) | |
| tree | 9ba8760c4b488879674cfa715ac0b5fff1f4b36c /src/mem/cache/queue.hh | |
| parent | 7d990bd25b478d906442ea63e1de6b381b51817b (diff) | |
| download | gem5-51056cec69a72931a319e7be9370ea63f18e1aa3.tar.xz | |
mem-cache: Add a non-coherent cache
The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.
This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>
Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
Reviewed-on: https://gem5-review.googlesource.com/8291
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Diffstat (limited to 'src/mem/cache/queue.hh')
| -rw-r--r-- | src/mem/cache/queue.hh | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/mem/cache/queue.hh b/src/mem/cache/queue.hh index f6941e64a..f603ea84e 100644 --- a/src/mem/cache/queue.hh +++ b/src/mem/cache/queue.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013, 2015-2016 ARM Limited + * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -148,12 +148,15 @@ class Queue : public Drainable } /** - * Find the first WriteQueueEntry that matches the provided address. + * Find the first entry that matches the provided address. + * * @param blk_addr The block address to find. * @param is_secure True if the target memory space is secure. + * @param ignore_uncacheable Should uncacheables be ignored or not * @return Pointer to the matching WriteQueueEntry, null if not found. */ - Entry* findMatch(Addr blk_addr, bool is_secure) const + Entry* findMatch(Addr blk_addr, bool is_secure, + bool ignore_uncacheable = true) const { for (const auto& entry : allocatedList) { // we ignore any entries allocated for uncacheable @@ -162,8 +165,8 @@ class Queue : public Drainable // uncacheable entries, and we do not want normal // cacheable accesses being added to an WriteQueueEntry // serving an uncacheable access - if (!entry->isUncacheable() && entry->blkAddr == blk_addr && - entry->isSecure == is_secure) { + if (!(ignore_uncacheable && entry->isUncacheable()) && + entry->blkAddr == blk_addr && entry->isSecure == is_secure) { return entry; } } |