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author | Sophiane Senni <sophiane.senni@gmail.com> | 2016-11-30 17:10:27 -0500 |
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committer | Sophiane Senni <sophiane.senni@gmail.com> | 2016-11-30 17:10:27 -0500 |
commit | ce2722cdd97a31f85d36f6c32637b230e3c25c73 (patch) | |
tree | 72993532267d3f1f99e8519be837dd7c523a722f /src/mem/cache/tags/Tags.py | |
parent | 047caf24ba9a640247b63584c2291e760f1f4d54 (diff) | |
download | gem5-ce2722cdd97a31f85d36f6c32637b230e3c25c73.tar.xz |
mem: Split the hit_latency into tag_latency and data_latency
If the cache access mode is parallel, i.e. "sequential_access" parameter
is set to "False", tags and data are accessed in parallel. Therefore,
the hit_latency is the maximum latency between tag_latency and
data_latency. On the other hand, if the cache access mode is
sequential, i.e. "sequential_access" parameter is set to "True",
tags and data are accessed sequentially. Therefore, the hit_latency
is the sum of tag_latency plus data_latency.
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/mem/cache/tags/Tags.py')
-rw-r--r-- | src/mem/cache/tags/Tags.py | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py index ab1282ac9..6c0b85044 100644 --- a/src/mem/cache/tags/Tags.py +++ b/src/mem/cache/tags/Tags.py @@ -49,17 +49,22 @@ class BaseTags(ClockedObject): # Get the block size from the parent (system) block_size = Param.Int(Parent.cache_line_size, "block size in bytes") - # Get the hit latency from the parent (cache) - hit_latency = Param.Cycles(Parent.hit_latency, - "The hit latency for this cache") + # Get the tag lookup latency from the parent (cache) + tag_latency = Param.Cycles(Parent.tag_latency, + "The tag lookup latency for this cache") + + # Get the RAM access latency from the parent (cache) + data_latency = Param.Cycles(Parent.data_latency, + "The data access latency for this cache") + + sequential_access = Param.Bool(Parent.sequential_access, + "Whether to access tags and data sequentially") class BaseSetAssoc(BaseTags): type = 'BaseSetAssoc' abstract = True cxx_header = "mem/cache/tags/base_set_assoc.hh" assoc = Param.Int(Parent.assoc, "associativity") - sequential_access = Param.Bool(Parent.sequential_access, - "Whether to access tags and data sequentially") class LRU(BaseSetAssoc): type = 'LRU' |