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authorSophiane Senni <sophiane.senni@gmail.com>2016-11-30 17:10:27 -0500
committerSophiane Senni <sophiane.senni@gmail.com>2016-11-30 17:10:27 -0500
commitce2722cdd97a31f85d36f6c32637b230e3c25c73 (patch)
tree72993532267d3f1f99e8519be837dd7c523a722f /src/mem/cache/tags/base_set_assoc.hh
parent047caf24ba9a640247b63584c2291e760f1f4d54 (diff)
downloadgem5-ce2722cdd97a31f85d36f6c32637b230e3c25c73.tar.xz
mem: Split the hit_latency into tag_latency and data_latency
If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/mem/cache/tags/base_set_assoc.hh')
-rw-r--r--src/mem/cache/tags/base_set_assoc.hh17
1 files changed, 12 insertions, 5 deletions
diff --git a/src/mem/cache/tags/base_set_assoc.hh b/src/mem/cache/tags/base_set_assoc.hh
index 31284991f..a6dcf0572 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -208,7 +208,6 @@ public:
Addr tag = extractTag(addr);
int set = extractSet(addr);
BlkType *blk = sets[set].findBlk(tag, is_secure);
- lat = accessLatency;;
// Access all tags in parallel, hence one in each way. The data side
// either accesses all blocks in parallel, or one block sequentially on
@@ -223,12 +222,20 @@ public:
}
if (blk != nullptr) {
- if (blk->whenReady > curTick()
- && cache->ticksToCycles(blk->whenReady - curTick())
- > accessLatency) {
- lat = cache->ticksToCycles(blk->whenReady - curTick());
+ // If a cache hit
+ lat = accessLatency;
+ // Check if the block to be accessed is available. If not,
+ // apply the accessLatency on top of block->whenReady.
+ if (blk->whenReady > curTick() &&
+ cache->ticksToCycles(blk->whenReady - curTick()) >
+ accessLatency) {
+ lat = cache->ticksToCycles(blk->whenReady - curTick()) +
+ accessLatency;
}
blk->refCount += 1;
+ } else {
+ // If a cache miss
+ lat = lookupLatency;
}
return blk;