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author | Prakash Ramrakhyani <prakash.ramrakhyani@arm.com> | 2013-06-27 05:49:50 -0400 |
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committer | Prakash Ramrakhyani <prakash.ramrakhyani@arm.com> | 2013-06-27 05:49:50 -0400 |
commit | ac515d7a9b131ffc9e128bd209fcddb2f383808b (patch) | |
tree | 4a445dffeed869dac321abc09b04d7c3d65601fe /src/mem/cache/tags/cacheset.hh | |
parent | 0d68d36b9d12c36e6201fa8bc4bec34258c04eab (diff) | |
download | gem5-ac515d7a9b131ffc9e128bd209fcddb2f383808b.tar.xz |
mem: Reorganize cache tags and make them a SimObject
This patch reorganizes the cache tags to allow more flexibility to
implement new replacement policies. The base tags class is now a
clocked object so that derived classes can use a clock if they need
one. Also having deriving from SimObject allows specialized Tag
classes to be swapped in/out in .py files.
The cache set is now templatized to allow it to contain customized
cache blocks with additional informaiton. This involved moving code to
the .hh file and removing cacheset.cc.
The statistics belonging to the cache tags are now including ".tags"
in their name. Hence, the stats need an update to reflect the change
in naming.
Diffstat (limited to 'src/mem/cache/tags/cacheset.hh')
-rw-r--r-- | src/mem/cache/tags/cacheset.hh | 102 |
1 files changed, 96 insertions, 6 deletions
diff --git a/src/mem/cache/tags/cacheset.hh b/src/mem/cache/tags/cacheset.hh index d38a1e927..31eb28bf0 100644 --- a/src/mem/cache/tags/cacheset.hh +++ b/src/mem/cache/tags/cacheset.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2013 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * @@ -43,6 +55,7 @@ /** * An associative set of cache blocks. */ +template <class Blktype> class CacheSet { public: @@ -50,28 +63,105 @@ class CacheSet int assoc; /** Cache blocks in this set, maintained in LRU order 0 = MRU. */ - CacheBlk **blks; + Blktype **blks; /** * Find a block matching the tag in this set. - * @param asid The address space ID. + * @param way_id The id of the way that matches the tag. * @param tag The Tag to find. - * @return Pointer to the block if found. + * @return Pointer to the block if found. Set way_id to assoc if none found */ - CacheBlk* findBlk(Addr tag) const; + Blktype* findBlk(Addr tag, int& way_id) const ; + Blktype* findBlk(Addr tag) const ; /** * Move the given block to the head of the list. * @param blk The block to move. */ - void moveToHead(CacheBlk *blk); + void moveToHead(Blktype *blk); /** * Move the given block to the tail of the list. * @param blk The block to move */ - void moveToTail(CacheBlk *blk); + void moveToTail(Blktype *blk); }; +template <class Blktype> +Blktype* +CacheSet<Blktype>::findBlk(Addr tag, int& way_id) const +{ + /** + * Way_id returns the id of the way that matches the block + * If no block is found way_id is set to assoc. + */ + way_id = assoc; + for (int i = 0; i < assoc; ++i) { + if (blks[i]->tag == tag && blks[i]->isValid()) { + way_id = i; + return blks[i]; + } + } + return NULL; +} + +template <class Blktype> +Blktype* +CacheSet<Blktype>::findBlk(Addr tag) const +{ + int ignored_way_id; + return findBlk(tag, ignored_way_id); +} + +template <class Blktype> +void +CacheSet<Blktype>::moveToHead(Blktype *blk) +{ + // nothing to do if blk is already head + if (blks[0] == blk) + return; + + // write 'next' block into blks[i], moving up from MRU toward LRU + // until we overwrite the block we moved to head. + + // start by setting up to write 'blk' into blks[0] + int i = 0; + Blktype *next = blk; + + do { + assert(i < assoc); + // swap blks[i] and next + Blktype *tmp = blks[i]; + blks[i] = next; + next = tmp; + ++i; + } while (next != blk); +} + +template <class Blktype> +void +CacheSet<Blktype>::moveToTail(Blktype *blk) +{ + // nothing to do if blk is already tail + if (blks[assoc - 1] == blk) + return; + + // write 'next' block into blks[i], moving from LRU to MRU + // until we overwrite the block we moved to tail. + + // start by setting up to write 'blk' into tail + int i = assoc - 1; + Blktype *next = blk; + + do { + assert(i >= 0); + // swap blks[i] and next + Blktype *tmp = blks[i]; + blks[i] = next; + next = tmp; + --i; + } while (next != blk); +} + #endif |