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authorPrakash Ramrakhyani <prakash.ramrakhyani@arm.com>2013-06-27 05:49:50 -0400
committerPrakash Ramrakhyani <prakash.ramrakhyani@arm.com>2013-06-27 05:49:50 -0400
commitac515d7a9b131ffc9e128bd209fcddb2f383808b (patch)
tree4a445dffeed869dac321abc09b04d7c3d65601fe /src/mem/cache/tags/fa_lru.hh
parent0d68d36b9d12c36e6201fa8bc4bec34258c04eab (diff)
downloadgem5-ac515d7a9b131ffc9e128bd209fcddb2f383808b.tar.xz
mem: Reorganize cache tags and make them a SimObject
This patch reorganizes the cache tags to allow more flexibility to implement new replacement policies. The base tags class is now a clocked object so that derived classes can use a clock if they need one. Also having deriving from SimObject allows specialized Tag classes to be swapped in/out in .py files. The cache set is now templatized to allow it to contain customized cache blocks with additional informaiton. This involved moving code to the .hh file and removing cacheset.cc. The statistics belonging to the cache tags are now including ".tags" in their name. Hence, the stats need an update to reflect the change in naming.
Diffstat (limited to 'src/mem/cache/tags/fa_lru.hh')
-rw-r--r--src/mem/cache/tags/fa_lru.hh23
1 files changed, 9 insertions, 14 deletions
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index 3c8cc5bec..3fbb8f0f4 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -54,6 +54,7 @@
#include "mem/cache/tags/base.hh"
#include "mem/cache/blk.hh"
#include "mem/packet.hh"
+#include "params/FALRU.hh"
/**
* A fully associative cache block.
@@ -92,13 +93,6 @@ class FALRU : public BaseTags
typedef std::list<FALRUBlk*> BlkList;
protected:
- /** The block size of the cache. */
- const unsigned blkSize;
- /** The size of the cache. */
- const unsigned size;
- /** The hit latency of the cache. */
- const Cycles hitLatency;
-
/** Array of pointers to blocks at the cache size boundaries. */
FALRUBlk **cacheBoundaries;
/** A mask for the FALRUBlk::inCache bits. */
@@ -161,20 +155,20 @@ class FALRU : public BaseTags
*/
public:
+
+ typedef FALRUParams Params;
+
/**
* Construct and initialize this cache tagstore.
- * @param blkSize The block size of the cache.
- * @param size The size of the cache.
- * @param hit_latency The hit latency of the cache.
*/
- FALRU(unsigned blkSize, unsigned size, Cycles hit_latency);
+ FALRU(const Params *p);
~FALRU();
/**
* Register the stats for this object.
* @param name The name to prepend to the stats name.
*/
- void regStats(const std::string &name);
+ void regStats();
/**
* Invalidate a cache block.
@@ -211,7 +205,7 @@ public:
*/
FALRUBlk* findVictim(Addr addr, PacketList & writebacks);
- void insertBlock(Addr addr, BlkType *blk, int context_src);
+ void insertBlock(PacketPtr pkt, BlkType *blk);
/**
* Return the hit latency of this cache.
@@ -324,6 +318,7 @@ public:
return;
}
}
+
};
#endif // __MEM_CACHE_TAGS_FA_LRU_HH__