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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:10:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:10:54 -0400 |
| commit | 88554790c34f6fef4ba6285927fb9742b90ab258 (patch) | |
| tree | 402fe474613aea36065f773f410d431637592955 /src/mem/cache/tags/iic.hh | |
| parent | d17f5084ed93efd6bdb3ed46b2f81b9d1240af8c (diff) | |
| download | gem5-88554790c34f6fef4ba6285927fb9742b90ab258.tar.xz | |
Mem: Use cycles to express cache-related latencies
This patch changes the cache-related latencies from an absolute time
expressed in Ticks, to a number of cycles that can be scaled with the
clock period of the caches. Ultimately this patch serves to enable
future work that involves dynamic frequency scaling. As an immediate
benefit it also makes it more convenient to specify cache performance
without implicitly assuming a specific CPU core operating frequency.
The stat blocked_cycles that actually counter in ticks is now updated
to count in cycles.
As the timing is now rounded to the clock edges of the cache, there
are some regressions that change. Plenty of them have very minor
changes, whereas some regressions with a short run-time are perturbed
quite significantly. A follow-on patch updates all the statistics for
the regressions.
Diffstat (limited to 'src/mem/cache/tags/iic.hh')
| -rw-r--r-- | src/mem/cache/tags/iic.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh index 97011d1c5..91e947704 100644 --- a/src/mem/cache/tags/iic.hh +++ b/src/mem/cache/tags/iic.hh @@ -176,7 +176,7 @@ class IIC : public BaseTags /** The associativity of the primary table. */ const unsigned assoc; /** The base hit latency. */ - const unsigned hitLatency; + const Cycles hitLatency; /** The subblock size, used for compression. */ const unsigned subSize; @@ -278,9 +278,9 @@ class IIC : public BaseTags /** The associativity of the primary table. */ unsigned assoc; /** The number of cycles for each hash lookup. */ - unsigned hashDelay; + Cycles hashDelay; /** The number of cycles to read the data. */ - unsigned hitLatency; + Cycles hitLatency; /** The replacement policy. */ Repl *rp; /** The subblock size in bytes. */ @@ -420,7 +420,7 @@ class IIC : public BaseTags * @param lat The access latency. * @return A pointer to the block found, if any. */ - IICTag* accessBlock(Addr addr, int &lat, int context_src); + IICTag* accessBlock(Addr addr, Cycles &lat, int context_src); /** * Find the block, do not update the replacement data. |