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author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-17 17:27:53 -0700 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-17 17:27:53 -0700 |
commit | 35cf19d441ed15d054d00674ec67ab5bc769f6d7 (patch) | |
tree | 86a97bf419e3c46834a446039ef8f4a85f74b7cc /src/mem/cache/tags/iic.hh | |
parent | a9b7c558fd6c00dacbdf36f4617c03a19c198b08 (diff) | |
download | gem5-35cf19d441ed15d054d00674ec67ab5bc769f6d7.tar.xz |
More major reorg of cache. Seems to work for atomic mode now,
timing mode still broken.
configs/example/memtest.py:
Revamp options.
src/cpu/memtest/memtest.cc:
No need for memory initialization.
No need to make atomic response... memory system should do that now.
src/cpu/memtest/memtest.hh:
MemTest really doesn't want to snoop.
src/mem/bridge.cc:
checkFunctional() cleanup.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/miss/SConscript:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/tport.cc:
More major reorg. Seems to work for atomic mode now,
timing mode still broken.
--HG--
extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
Diffstat (limited to 'src/mem/cache/tags/iic.hh')
-rw-r--r-- | src/mem/cache/tags/iic.hh | 27 |
1 files changed, 1 insertions, 26 deletions
diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh index d0663d330..082b3d15e 100644 --- a/src/mem/cache/tags/iic.hh +++ b/src/mem/cache/tags/iic.hh @@ -345,17 +345,6 @@ class IIC : public BaseTags return hitLatency; } - /** - * Generate the tag from the address. - * @param addr The address to a get a tag for. - * @param blk Ignored here. - * @return the tag. - */ - Addr extractTag(Addr addr, IICTag *blk) const - { - return (addr >> tagShift); - } - /** * Generate the tag from the address. * @param addr The address to a get a tag for. @@ -423,18 +412,6 @@ class IIC : public BaseTags } /** - * Decompress a block if it is compressed. - * @param index The tag store index for the block to uncompress. - */ - void decompressBlock(unsigned long index); - - /** - * Try and compress a block if it is not already compressed. - * @param index The tag store index for the block to compress. - */ - void compressBlock(unsigned long index); - - /** * Invalidate a block. * @param blk The block to invalidate. */ @@ -462,11 +439,9 @@ class IIC : public BaseTags * Find a replacement block for the address provided. * @param pkt The request to a find a replacement candidate for. * @param writebacks List for any writebacks to be performed. - * @param compress_blocks List of blocks to compress, for adaptive comp. * @return The block to place the replacement in. */ - IICTag* findReplacement(PacketPtr &pkt, PacketList &writebacks, - BlkList &compress_blocks); + IICTag* findReplacement(Addr addr, PacketList &writebacks); /** * Read the data from the internal storage of the given cache block. |