AtomicSimpleCPU with a cache now runs the hello world! test program.

Need to clean up a bunch of flags/hacks in the code.  Then onto Timming mode.

Functional accesses also work properly, although not exactly how we wanted them.  I'll need to clean that up as well.

src/cpu/simple/atomic.cc:
    Atomic CPU needs to set thread context so stats work in cache.  Temporarily just use CPU=0 ThreadID=0
src/mem/cache/cache_impl.hh:
    Need to return success/failure properly still
    Physical memory object doesn't assert SATISFIED anymore, need to remove that flag
src/mem/cache/tags/lru.cc:
    Doesn't work if the REQ doesn't set it's ASID.  Temporary fix use 0 always

--HG--
extra : convert_revision : d06a39684af593db699b64df9a29f80c61d8d050

1 files changed, 1 insertions, 1 deletions

diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index b7259bd3a..556025a3a 100644
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -188,7 +188,7 @@ LRUBlk*
 LRU::findBlock(Packet * &pkt, int &lat)
 {
     Addr addr = pkt->getAddr();
-    int asid = pkt->req->getAsid();
+    int asid = 0;//pkt->req->getAsid();
 
     Addr tag = extractTag(addr);
     unsigned set = extractSet(addr);