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author | Daniel R. Carvalho <odanrc@yahoo.com.br> | 2018-02-19 15:13:11 +0100 |
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committer | Daniel Carvalho <odanrc@yahoo.com.br> | 2018-03-22 14:50:23 +0000 |
commit | d207e9ccee411877fdeac80bb68a27900560f50f (patch) | |
tree | 120810cf72c52ed5df29436552e06f1fb11aa5ce /src/mem/cache/tags/random_repl.cc | |
parent | 0473286ab1e9992a906eff380000bf90c82eeccb (diff) | |
download | gem5-d207e9ccee411877fdeac80bb68a27900560f50f.tar.xz |
mem-cache: Split array indexing and replacement policies.
Replacement policies (LRU, Random) are currently considered as array
indexing methods, but have completely different functionalities:
- Array indexers determine the possible locations for block allocation.
This information is used to generate replacement candidates when
conflicts happen.
- Replacement policies determine which of the replacement candidates
should be evicted to make room for new allocations.
For this reason, they were split into different classes. Advantages:
- Easier and more straightforward to implement other replacement
policies (RRIP, LFU, ARC, ...)
- Allow easier future implementation of cache organization schemes
As now we can't assure the use of sets, the previous way to create a
true LRU is not viable. Now a timestamp_bits parameter controls how
many bits are dedicated for the timestamp, and a true LRU can be
achieved through an infinite number of bits (although a few bits suffice
in practice).
Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda
Reviewed-on: https://gem5-review.googlesource.com/8501
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/mem/cache/tags/random_repl.cc')
-rw-r--r-- | src/mem/cache/tags/random_repl.cc | 105 |
1 files changed, 0 insertions, 105 deletions
diff --git a/src/mem/cache/tags/random_repl.cc b/src/mem/cache/tags/random_repl.cc deleted file mode 100644 index aa5f6fcb9..000000000 --- a/src/mem/cache/tags/random_repl.cc +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) 2017 ARM Limited - * All rights reserved. - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Copyright (c) 2014 The Regents of The University of Michigan - * Copyright (c) 2016 ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Anthony Gutierrez - */ - -/** - * @file - * Definitions of a random replacement tag store. - */ - -#include "mem/cache/tags/random_repl.hh" - -#include "base/random.hh" -#include "debug/CacheRepl.hh" -#include "mem/cache/base.hh" - -RandomRepl::RandomRepl(const Params *p) - : BaseSetAssoc(p) - -{ -} - -CacheBlk* -RandomRepl::accessBlock(Addr addr, bool is_secure, Cycles &lat) -{ - return BaseSetAssoc::accessBlock(addr, is_secure, lat); -} - -CacheBlk* -RandomRepl::findVictim(Addr addr) -{ - CacheBlk *blk = BaseSetAssoc::findVictim(addr); - unsigned set = extractSet(addr); - - // if all blocks are valid, pick a replacement at random - if (blk && blk->isValid()) { - // find a random index within the bounds of the set - int idx = random_mt.random<int>(0, assoc - 1); - blk = sets[set].blks[idx]; - // Enforce allocation limit - while (blk->way >= allocAssoc) { - idx = (idx + 1) % assoc; - blk = sets[set].blks[idx]; - } - - assert(idx < assoc); - assert(idx >= 0); - assert(blk->way < allocAssoc); - - DPRINTF(CacheRepl, "set %x: selecting blk %x for replacement\n", - blk->set, regenerateBlkAddr(blk)); - } - - return blk; -} - -void -RandomRepl::insertBlock(PacketPtr pkt, BlkType *blk) -{ - BaseSetAssoc::insertBlock(pkt, blk); -} - -RandomRepl* -RandomReplParams::create() -{ - return new RandomRepl(this); -} |