diff options
author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2016-05-26 11:56:24 +0100 |
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committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2016-05-26 11:56:24 +0100 |
commit | d68f3577d6183de7dcadc1cfbfe53444e83989de (patch) | |
tree | 4bacf524b307b385a74b237c0a2de0b0234908cc /src/mem/cache/tags | |
parent | 90bf50b4c7249a4f5529245a82bc59370de468bd (diff) | |
download | gem5-d68f3577d6183de7dcadc1cfbfe53444e83989de.tar.xz |
mem: change NULL to nullptr in the cache related classes
Change-Id: I5042410be54935650b7d05c84d8d9efbfcc06e70
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/mem/cache/tags')
-rw-r--r-- | src/mem/cache/tags/base_set_assoc.hh | 8 | ||||
-rw-r--r-- | src/mem/cache/tags/cacheset.hh | 2 | ||||
-rw-r--r-- | src/mem/cache/tags/fa_lru.cc | 16 | ||||
-rw-r--r-- | src/mem/cache/tags/fa_lru.hh | 4 | ||||
-rw-r--r-- | src/mem/cache/tags/lru.cc | 4 |
5 files changed, 17 insertions, 17 deletions
diff --git a/src/mem/cache/tags/base_set_assoc.hh b/src/mem/cache/tags/base_set_assoc.hh index 910d44b36..053274c53 100644 --- a/src/mem/cache/tags/base_set_assoc.hh +++ b/src/mem/cache/tags/base_set_assoc.hh @@ -193,7 +193,7 @@ public: /** * Access block and update replacement data. May not succeed, in which case - * NULL pointer is returned. This has all the implications of a cache + * nullptr is returned. This has all the implications of a cache * access and should only be used as such. Returns the access latency as a * side effect. * @param addr The address to find. @@ -215,14 +215,14 @@ public: // a hit. Sequential access with a miss doesn't access data. tagAccesses += allocAssoc; if (sequentialAccess) { - if (blk != NULL) { + if (blk != nullptr) { dataAccesses += 1; } } else { dataAccesses += allocAssoc; } - if (blk != NULL) { + if (blk != nullptr) { if (blk->whenReady > curTick() && cache->ticksToCycles(blk->whenReady - curTick()) > accessLatency) { @@ -253,7 +253,7 @@ public: */ CacheBlk* findVictim(Addr addr) override { - BlkType *blk = NULL; + BlkType *blk = nullptr; int set = extractSet(addr); // prefer to evict an invalid block diff --git a/src/mem/cache/tags/cacheset.hh b/src/mem/cache/tags/cacheset.hh index 71a69b3dc..8bf0989f7 100644 --- a/src/mem/cache/tags/cacheset.hh +++ b/src/mem/cache/tags/cacheset.hh @@ -104,7 +104,7 @@ CacheSet<Blktype>::findBlk(Addr tag, bool is_secure, int& way_id) const return blks[i]; } } - return NULL; + return nullptr; } template <class Blktype> diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc index c9531d12c..ecac88afa 100644 --- a/src/mem/cache/tags/fa_lru.cc +++ b/src/mem/cache/tags/fa_lru.cc @@ -79,12 +79,12 @@ FALRU::FALRU(const Params *p) head = &(blks[0]); tail = &(blks[numBlocks-1]); - head->prev = NULL; + head->prev = nullptr; head->next = &(blks[1]); head->inCache = cacheMask; tail->prev = &(blks[numBlocks-2]); - tail->next = NULL; + tail->next = nullptr; tail->inCache = 0; unsigned index = (1 << 17) / blkSize; @@ -159,7 +159,7 @@ FALRU::hashLookup(Addr addr) const if (iter != tagHash.end()) { return (*iter).second; } - return NULL; + return nullptr; } void @@ -199,7 +199,7 @@ FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src, moveToHead(blk); } } else { - blk = NULL; + blk = nullptr; for (unsigned i = 0; i <= numCaches; ++i) { misses[i]++; } @@ -223,7 +223,7 @@ FALRU::findBlock(Addr addr, bool is_secure) const if (blk && blk->isValid()) { assert(blk->tag == blkAddr); } else { - blk = NULL; + blk = nullptr; } return blk; } @@ -277,15 +277,15 @@ FALRU::moveToHead(FALRUBlk *blk) blk->inCache = cacheMask; if (blk != head) { if (blk == tail){ - assert(blk->next == NULL); + assert(blk->next == nullptr); tail = blk->prev; - tail->next = NULL; + tail->next = nullptr; } else { blk->prev->next = blk->next; blk->next->prev = blk->prev; } blk->next = head; - blk->prev = NULL; + blk->prev = nullptr; head->prev = blk; head = blk; } diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index 0dd402cea..ecfe467ef 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -178,8 +178,8 @@ public: /** * Access block and update replacement data. May not succeed, in which - * case NULL pointer is returned. This has all the implications of a cache - * access and should only be used as such. + * case nullptr pointer is returned. This has all the implications of a + * cache access and should only be used as such. * Returns the access latency and inCache flags as a side effect. * @param addr The address to look for. * @param is_secure True if the target memory space is secure. diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc index 31423f994..a85b63889 100644 --- a/src/mem/cache/tags/lru.cc +++ b/src/mem/cache/tags/lru.cc @@ -59,7 +59,7 @@ LRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int master_id) { CacheBlk *blk = BaseSetAssoc::accessBlock(addr, is_secure, lat, master_id); - if (blk != NULL) { + if (blk != nullptr) { // move this block to head of the MRU list sets[blk->set].moveToHead(blk); DPRINTF(CacheRepl, "set %x: moving blk %x (%s) to MRU\n", @@ -75,7 +75,7 @@ LRU::findVictim(Addr addr) { int set = extractSet(addr); // grab a replacement candidate - BlkType *blk = NULL; + BlkType *blk = nullptr; for (int i = assoc - 1; i >= 0; i--) { BlkType *b = sets[set].blks[i]; if (b->way < allocAssoc) { |