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| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-21 04:48:06 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-21 04:48:06 -0400 |
| commit | 6c92ee49f1125559ffc7c20cfe96306b9c4de017 (patch) | |
| tree | 2c74e0d43480d725ed436145a5c5ce93b105d824 /src/mem/cache/write_queue.cc | |
| parent | 53d735b17ee1a3bd27173138ed1937a45f20bc12 (diff) | |
| download | gem5-6c92ee49f1125559ffc7c20cfe96306b9c4de017.tar.xz | |
mem: Align downstream cache packet creation in atomic and timing
This patch makes the control flow more uniform in atomic and timing,
ultimately making the code easier to understand.
Diffstat (limited to 'src/mem/cache/write_queue.cc')
0 files changed, 0 insertions, 0 deletions