diff options
author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2016-05-31 18:03:42 +0100 |
---|---|---|
committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-05 11:47:01 +0000 |
commit | 2f6d69ee08bd92d9fcfb9b78f84b2d7c0ba113d0 (patch) | |
tree | 8c4a2a779948fd5a9cac10635627e1e6075cf4b1 /src/mem/cache/write_queue_entry.cc | |
parent | d8afb8679301392561f4255edb9789d22aec5a2e (diff) | |
download | gem5-2f6d69ee08bd92d9fcfb9b78f84b2d7c0ba113d0.tar.xz |
mem: Add support for WriteClean packets in the memory system
This change adds support for creating and handling WriteClean
packets. The WriteClean operation is almost identical to a
WritebackDirty with the exception that the cache generating a
WriteClean retains a copy of the block.
Change-Id: I63c8de62919fad0f9547d412f8266aa4292ebecd
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5045
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/mem/cache/write_queue_entry.cc')
-rw-r--r-- | src/mem/cache/write_queue_entry.cc | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mem/cache/write_queue_entry.cc b/src/mem/cache/write_queue_entry.cc index 7a778ea72..663c231fa 100644 --- a/src/mem/cache/write_queue_entry.cc +++ b/src/mem/cache/write_queue_entry.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013, 2015-2016 ARM Limited + * Copyright (c) 2012-2013, 2015-2017 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -111,9 +111,10 @@ WriteQueueEntry::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target, "Write queue entry %#llx should never have more than one " "cacheable target", blkAddr); panic_if(!((target->isWrite() && _isUncacheable) || - (target->isEviction() && !_isUncacheable)), - "Write queue entry %#llx should either be uncacheable write or " - "a cacheable eviction"); + (target->isEviction() && !_isUncacheable) || + target->cmd == MemCmd::WriteClean), + "Write queue entry %#llx should be an uncacheable write or " + "a cacheable eviction or a writeclean"); targets.add(target, when_ready, _order); } |