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authorNikos Nikoleris <nikos.nikoleris@arm.com>2018-02-02 17:34:40 +0000
committerNikos Nikoleris <nikos.nikoleris@arm.com>2018-05-31 15:12:04 +0000
commit41db9b95aa234094da62fdd3a863870b175d8f97 (patch)
tree433ad327b0e148bbacc65e1fcfdb87e41f1c4cb4 /src/mem/cache/write_queue_entry.hh
parentd5c4dd986a48f13cc774e487993634d8c2b68e10 (diff)
downloadgem5-41db9b95aa234094da62fdd3a863870b175d8f97.tar.xz
mem-cache: Adopt a more sensible cache class hierarchy
This patch changes what goes into the BaseCache and what goes into the Cache, to make it easier to add a NoncoherentCache with as much re-use as possible. A number of redundant members and definitions are also removed in the process. This is a modified version of a changeset put together by Andreas Hansson <andreas.hansson@arm.com> Change-Id: Ie9dd73c4ec07732e778e7416b712dad8b4bd5d4b Reviewed-on: https://gem5-review.googlesource.com/10431 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/mem/cache/write_queue_entry.hh')
-rw-r--r--src/mem/cache/write_queue_entry.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/write_queue_entry.hh b/src/mem/cache/write_queue_entry.hh
index 13dd09bf6..40079b4ca 100644
--- a/src/mem/cache/write_queue_entry.hh
+++ b/src/mem/cache/write_queue_entry.hh
@@ -54,7 +54,7 @@
#include "base/printable.hh"
#include "mem/cache/queue_entry.hh"
-class Cache;
+class BaseCache;
/**
* Write queue entry
@@ -101,7 +101,7 @@ class WriteQueueEntry : public QueueEntry, public Printable
/** WriteQueueEntry list iterator. */
typedef List::iterator Iterator;
- bool sendPacket(Cache &cache);
+ bool sendPacket(BaseCache &cache);
private: