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authorRon Dreslinski <rdreslin@umich.edu>2006-10-19 21:26:46 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-19 21:26:46 -0400
commit780aa0a0ebb765781a31d0fb58257b1efb1f324a (patch)
treeae6dbaca9ea90d3fa7ed3b16c633229a7f995dd0 /src/mem/cache
parentcc1feb9f6ddf9d0a58365ffa9f7ae948bf19901d (diff)
downloadgem5-780aa0a0ebb765781a31d0fb58257b1efb1f324a.tar.xz
Fix corner case on assertion.
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere. Still a functional access bug someplace I need to track down in timing mode. src/mem/cache/base_cache.cc: src/mem/cache/cache_impl.hh: Fix corner case on assertion tests/configs/memtest.py: Updated memtester with uncacheable addresses and functional accesses --HG-- extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/base_cache.cc2
-rw-r--r--src/mem/cache/cache_impl.hh4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 936a9c1fa..e0301a757 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -132,7 +132,7 @@ BaseCache::CachePort::recvFunctional(Packet *pkt)
pkt_data = pkt->getPtr<uint8_t>() + offset;
write_data = target->getPtr<uint8_t>();
data_size = pkt->getSize() - offset;
- assert(data_size > pkt->getSize());
+ assert(data_size >= pkt->getSize());
if (data_size > target->getSize())
data_size = target->getSize();
}
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index d8afcb009..ea30dbba6 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -585,7 +585,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
pkt_data = pkt->getPtr<uint8_t>() + offset;
write_data = target->getPtr<uint8_t>();
data_size = pkt->getSize() - offset;
- assert(data_size > pkt->getSize());
+ assert(data_size >= pkt->getSize());
if (data_size > target->getSize())
data_size = target->getSize();
}
@@ -620,7 +620,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
pkt_data = pkt->getPtr<uint8_t>() + offset;
write_data = write->getPtr<uint8_t>();
data_size = pkt->getSize() - offset;
- assert(data_size > pkt->getSize());
+ assert(data_size >= pkt->getSize());
if (data_size > write->getSize())
data_size = write->getSize();
}