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authorDaniel R. Carvalho <odanrc@yahoo.com.br>2018-12-05 15:06:56 +0100
committerDaniel Carvalho <odanrc@yahoo.com.br>2018-12-05 16:02:01 +0000
commit813e124c14c6a04f97bdf8b2defd84d0ca201f45 (patch)
tree149a14784b36cb2d59aba43bd0306fa0137d3bfe /src/mem/cache
parent174da8e2da6a896d2e97bc264f9c827a0f4c35ac (diff)
downloadgem5-813e124c14c6a04f97bdf8b2defd84d0ca201f45.tar.xz
mem-cache: Remove writebacks parameter from serviceMSHRTargets
Change 8ba77ae8fc98a355082da2bd9fdc6ecf4928f725 introduced the writebacks parameter, but it was never used. Change-Id: I225e5b399de42d77c72fc0012d3dc93ef39b8853 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14896 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/base.cc2
-rw-r--r--src/mem/cache/base.hh6
-rw-r--r--src/mem/cache/cache.cc3
-rw-r--r--src/mem/cache/cache.hh4
-rw-r--r--src/mem/cache/noncoherent_cache.cc2
-rw-r--r--src/mem/cache/noncoherent_cache.hh2
6 files changed, 8 insertions, 11 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index bad24f7ee..08cd09fc5 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -498,7 +498,7 @@ BaseCache::recvTimingResp(PacketPtr pkt)
mshr->promoteWritable();
}
- serviceMSHRTargets(mshr, pkt, blk, writebacks);
+ serviceMSHRTargets(mshr, pkt, blk);
if (mshr->promoteDeferredTargets()) {
// avoid later read getting stale data while write miss is
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 240bf216f..70b3d3e45 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -495,16 +495,14 @@ class BaseCache : public MemObject
* Service non-deferred MSHR targets using the received response
*
* Iterates through the list of targets that can be serviced with
- * the current response. Any writebacks that need to performed
- * must be appended to the writebacks parameter.
+ * the current response.
*
* @param mshr The MSHR that corresponds to the reponse
* @param pkt The response packet
* @param blk The reference block
- * @param writebacks List of writebacks that need to be performed
*/
virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
- CacheBlk *blk, PacketList& writebacks) = 0;
+ CacheBlk *blk) = 0;
/**
* Handles a response (cache line fill/write ack) from the bus.
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 624f244ce..90c4b9b5a 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -685,8 +685,7 @@ Cache::recvAtomic(PacketPtr pkt)
void
-Cache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk,
- PacketList &writebacks)
+Cache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk)
{
MSHR::Target *initial_tgt = mshr->getTarget();
// First offset for critical word first calculations
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index a7eb97d3b..33c5a2412 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -103,8 +103,8 @@ class Cache : public BaseCache
void doWritebacksAtomic(PacketList& writebacks) override;
- void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk,
- PacketList& writebacks) override;
+ void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
+ CacheBlk *blk) override;
void recvTimingSnoopReq(PacketPtr pkt) override;
diff --git a/src/mem/cache/noncoherent_cache.cc b/src/mem/cache/noncoherent_cache.cc
index 5edd435c6..ca282a38d 100644
--- a/src/mem/cache/noncoherent_cache.cc
+++ b/src/mem/cache/noncoherent_cache.cc
@@ -243,7 +243,7 @@ NoncoherentCache::functionalAccess(PacketPtr pkt, bool from_cpu_side)
void
NoncoherentCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
- CacheBlk *blk, PacketList &writebacks)
+ CacheBlk *blk)
{
MSHR::Target *initial_tgt = mshr->getTarget();
// First offset for critical word first calculations
diff --git a/src/mem/cache/noncoherent_cache.hh b/src/mem/cache/noncoherent_cache.hh
index 824c7ccc9..3da87d90e 100644
--- a/src/mem/cache/noncoherent_cache.hh
+++ b/src/mem/cache/noncoherent_cache.hh
@@ -86,7 +86,7 @@ class NoncoherentCache : public BaseCache
void doWritebacksAtomic(PacketList& writebacks) override;
void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
- CacheBlk *blk, PacketList& writebacks) override;
+ CacheBlk *blk) override;
void recvTimingResp(PacketPtr pkt) override;