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authorRon Dreslinski <rdreslin@umich.edu>2006-10-10 17:25:50 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-10 17:25:50 -0400
commitaff3d92c007f7c971eed8417b1d7602394755398 (patch)
tree2055d7ec8c7c5532a68cdece5b30f18621075a5c /src/mem/cache
parent995146ead7bcf03b80bdea6281fa4a225ad48b72 (diff)
downloadgem5-aff3d92c007f7c971eed8417b1d7602394755398.tar.xz
Some more code cleanup
src/mem/cache/base_cache.cc: Add sanity checks src/mem/cache/base_cache.hh: Fix for retry mechanism --HG-- extra : convert_revision : 9298e32e64194b1ef3fe51242595eaa56dcbbcfd
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/base_cache.cc2
-rw-r--r--src/mem/cache/base_cache.hh2
2 files changed, 3 insertions, 1 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 0141fa2a0..4df13fb2b 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -221,6 +221,7 @@ BaseCache::CacheEvent::process()
}
else if (!cachePort->isCpuSide)
{
+ assert(cachePort->cache->doMasterRequest());
//MSHR
pkt = cachePort->cache->getPacket();
MSHR* mshr = (MSHR*) pkt->senderState;
@@ -238,6 +239,7 @@ BaseCache::CacheEvent::process()
}
else
{
+ assert(cachePort->cache->doSlaveRequest());
//CSHR
pkt = cachePort->cache->getCoherencePacket();
bool success = cachePort->sendTiming(pkt);
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 41c28f3a1..563b1ca8b 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -467,7 +467,7 @@ class BaseCache : public MemObject
*/
void setMasterRequest(RequestCause cause, Tick time)
{
- if (!doMasterRequest() && memSidePort->drainList.empty())
+ if (!doMasterRequest() && !memSidePort->waitingOnRetry)
{
BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
reqCpu->schedule(time);