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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 21:44:15 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 21:44:15 -0700 |
| commit | bd6f2bb538b09ce221c46d1ec5d5bfbf9a1d3350 (patch) | |
| tree | 5492dc138704c1c3da4592a42f6a45be904e0188 /src/mem/cache | |
| parent | 089b3840865f816493a33f2ccf987307d0a79f87 (diff) | |
| download | gem5-bd6f2bb538b09ce221c46d1ec5d5bfbf9a1d3350.tar.xz | |
Mem: Change isLlsc to isLLSC.
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/blk.hh | 4 | ||||
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh index acb117f6c..ab15355bd 100644 --- a/src/mem/cache/blk.hh +++ b/src/mem/cache/blk.hh @@ -218,7 +218,7 @@ class CacheBlk */ void trackLoadLocked(PacketPtr pkt) { - assert(pkt->isLlsc()); + assert(pkt->isLLSC()); lockList.push_front(Lock(pkt->req)); } @@ -236,7 +236,7 @@ class CacheBlk bool checkWrite(PacketPtr pkt) { Request *req = pkt->req; - if (pkt->isLlsc()) { + if (pkt->isLLSC()) { // it's a store conditional... have to check for matching // load locked. bool success = false; diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index f98d6ac34..ea8ae0046 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -180,7 +180,7 @@ Cache<TagStore>::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk) pkt->writeDataToBlock(blk->data, blkSize); } } else if (pkt->isRead()) { - if (pkt->isLlsc()) { + if (pkt->isLLSC()) { blk->trackLoadLocked(pkt); } pkt->setDataFromBlock(blk->data, blkSize); @@ -317,7 +317,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk, incMissCount(pkt); - if (blk == NULL && pkt->isLlsc() && pkt->isWrite()) { + if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) { // complete miss on store conditional... just give up now pkt->req->setExtraData(0); return true; |