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| author | Gabe Black <gabeblack@google.com> | 2019-04-22 19:45:10 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-04-28 01:19:40 +0000 |
| commit | cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9 (patch) | |
| tree | 893cea35432466600b55a2e4434ed61ba1e28f69 /src/mem/cache | |
| parent | 3cfff8574a19536e2b3d057b43b59fcf35932c81 (diff) | |
| download | gem5-cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9.tar.xz | |
mem: Minimize the use of MemObject.
MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.
Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/Cache.py | 4 | ||||
| -rw-r--r-- | src/mem/cache/base.cc | 6 | ||||
| -rw-r--r-- | src/mem/cache/base.hh | 4 |
3 files changed, 7 insertions, 7 deletions
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py index 0a590c2ca..b2f478472 100644 --- a/src/mem/cache/Cache.py +++ b/src/mem/cache/Cache.py @@ -43,7 +43,7 @@ from m5.params import * from m5.proxy import * from m5.SimObject import SimObject -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject from m5.objects.Prefetcher import BasePrefetcher from m5.objects.ReplacementPolicies import * from m5.objects.Tags import * @@ -72,7 +72,7 @@ class WriteAllocator(SimObject): block_size = Param.Int(Parent.cache_line_size, "block size in bytes") -class BaseCache(MemObject): +class BaseCache(ClockedObject): type = 'BaseCache' abstract = True cxx_header = "mem/cache/base.hh" diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 554a61eb0..f087618c7 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -77,7 +77,7 @@ BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, } BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) - : MemObject(p), + : ClockedObject(p), cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"), memSidePort(p->name + ".mem_side", this, "MemSidePort"), mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below @@ -193,7 +193,7 @@ BaseCache::getPort(const std::string &if_name, PortID idx) } else if (if_name == "cpu_side") { return cpuSidePort; } else { - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } } @@ -1696,7 +1696,7 @@ BaseCache::unserialize(CheckpointIn &cp) void BaseCache::regStats() { - MemObject::regStats(); + ClockedObject::regStats(); using namespace Stats; diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 8d5ed11d0..b995a6e47 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -68,12 +68,12 @@ #include "mem/cache/tags/base.hh" #include "mem/cache/write_queue.hh" #include "mem/cache/write_queue_entry.hh" -#include "mem/mem_object.hh" #include "mem/packet.hh" #include "mem/packet_queue.hh" #include "mem/qport.hh" #include "mem/request.hh" #include "params/WriteAllocator.hh" +#include "sim/clocked_object.hh" #include "sim/eventq.hh" #include "sim/probe/probe.hh" #include "sim/serialize.hh" @@ -91,7 +91,7 @@ struct BaseCacheParams; /** * A basic cache interface. Implements some common functions for speed. */ -class BaseCache : public MemObject +class BaseCache : public ClockedObject { protected: /** |