MEM: Introduce the master/slave port sub-classes in C++

This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.

5 files changed, 30 insertions, 24 deletions

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index a2cb59a76..4ae6376db 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -57,7 +57,7 @@ using namespace std;
 BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
                                           BaseCache *_cache,
                                           const std::string &_label)
-    : QueuedPort(_name, _cache, queue), queue(*_cache, *this, _label),
+    : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label),
       blocked(false), mustSendRetry(false), sendRetryEvent(this)
 {
 }
@@ -99,7 +99,7 @@ BaseCache::CacheSlavePort::clearBlocked()
         DPRINTF(CachePort, "Cache port %s sending retry\n", name());
         mustSendRetry = false;
         // @TODO: need to find a better time (next bus cycle?)
-        owner->schedule(sendRetryEvent, curTick() + 1);
+        owner.schedule(sendRetryEvent, curTick() + 1);
     }
 }
 
@@ -108,10 +108,29 @@ void
 BaseCache::init()
 {
     if (!cpuSidePort->isConnected() || !memSidePort->isConnected())
-        panic("Cache %s not hooked up on both sides\n", name());
+        fatal("Cache ports on %s are not connected\n", name());
     cpuSidePort->sendRangeChange();
 }
 
+MasterPort &
+BaseCache::getMasterPort(const std::string &if_name, int idx)
+{
+    if (if_name == "mem_side") {
+        return *memSidePort;
+    }  else {
+        return MemObject::getMasterPort(if_name, idx);
+    }
+}
+
+SlavePort &
+BaseCache::getSlavePort(const std::string &if_name, int idx)
+{
+    if (if_name == "cpu_side") {
+        return *cpuSidePort;
+    } else {
+        return MemObject::getSlavePort(if_name, idx);
+    }
+}
 
 void
 BaseCache::regStats()
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index c13d27d42..47cbaf7a0 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -118,7 +118,7 @@ class BaseCache : public MemObject
      * and the sendDeferredPacket of the timing port is modified to
      * consider both the transmit list and the requests from the MSHR.
      */
-    class CacheMasterPort : public QueuedPort
+    class CacheMasterPort : public QueuedMasterPort
     {
 
       public:
@@ -149,7 +149,7 @@ class BaseCache : public MemObject
 
         CacheMasterPort(const std::string &_name, BaseCache *_cache,
                         PacketQueue &_queue) :
-            QueuedPort(_name, _cache, _queue)
+            QueuedMasterPort(_name, _cache, _queue)
         { }
 
         /**
@@ -157,7 +157,7 @@ class BaseCache : public MemObject
          *
          * @return always true
          */
-        virtual bool isSnooping() { return true; }
+        virtual bool isSnooping() const { return true; }
     };
 
     /**
@@ -168,7 +168,7 @@ class BaseCache : public MemObject
      * incoming requests. If blocked, the port will issue a retry once
      * unblocked.
      */
-    class CacheSlavePort : public QueuedPort
+    class CacheSlavePort : public QueuedSlavePort
     {
 
       public:
@@ -444,6 +444,9 @@ class BaseCache : public MemObject
 
     virtual void init();
 
+    virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
+    virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1);
+
     /**
      * Query block size of a cache.
      * @return  The block size
diff --git a/src/mem/cache/builder.cc b/src/mem/cache/builder.cc
index cc206b784..ca8c378fb 100644
--- a/src/mem/cache/builder.cc
+++ b/src/mem/cache/builder.cc
@@ -40,7 +40,6 @@
 #include "mem/cache/base.hh"
 #include "mem/cache/cache.hh"
 #include "mem/config/cache.hh"
-#include "mem/bus.hh"
 #include "params/BaseCache.hh"
 
 // Tag Templates
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 782749aab..e745529a7 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -249,8 +249,6 @@ class Cache : public BaseCache
     /** Instantiates a basic cache object. */
     Cache(const Params *p, TagStore *tags);
 
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
-
     void regStats();
 
     /**
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 2463071de..3525e0777 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -92,19 +92,6 @@ Cache<TagStore>::regStats()
 }
 
 template<class TagStore>
-Port *
-Cache<TagStore>::getPort(const std::string &if_name, int idx)
-{
-    if (if_name == "cpu_side") {
-        return cpuSidePort;
-    } else if (if_name == "mem_side") {
-        return memSidePort;
-    }  else {
-        panic("Port name %s unrecognized\n", if_name);
-    }
-}
-
-template<class TagStore>
 void
 Cache<TagStore>::cmpAndSwap(BlkType *blk, PacketPtr pkt)
 {
@@ -795,7 +782,7 @@ Cache<TagStore>::functionalAccess(PacketPtr pkt, bool fromCpuSide)
         // continues towards the memory side
         if (fromCpuSide) {
             memSidePort->sendFunctional(pkt);
-        } else if (forwardSnoops) {
+        } else if (forwardSnoops && cpuSidePort->getMasterPort().isSnooping()) {
             // if it came from the memory side, it must be a snoop request
             // and we should only forward it if we are forwarding snoops
             cpuSidePort->sendFunctional(pkt);