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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-21 12:03:22 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-21 12:03:22 -0700 |
| commit | eff122797b5bc735c6d7c797be691c0fa02032e3 (patch) | |
| tree | 1dd1cef3b2b4e044fece9a406cd0ce97d09a2da7 /src/mem/cache | |
| parent | 83af0fdcf57175adf8077c51e9ba872dd2c04b76 (diff) | |
| parent | 5195500cdf7dc99b5367f91387eef4e9f5b65bfe (diff) | |
| download | gem5-eff122797b5bc735c6d7c797be691c0fa02032e3.tar.xz | |
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
--HG--
extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/BaseCache.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 32f3f0174..55b68f81f 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -90,3 +90,4 @@ class BaseCache(MemObject): "Only prefetch on data not on instruction accesses") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") + addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes") |