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authorRon Dreslinski <rdreslin@umich.edu>2006-06-30 16:25:35 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-06-30 16:25:35 -0400
commit1bdc65b00f40b20dc5c7e97d3c8d8e4b311230a8 (patch)
tree0fe0173bf6a5d9c173d565f85698eb6a7b2e2e48 /src/mem/cache
parentdea1a19b2de2fe031f714904c5247cf27b363237 (diff)
downloadgem5-1bdc65b00f40b20dc5c7e97d3c8d8e4b311230a8.tar.xz
First pass, now compiles with current head of tree.
Compile and initialization work, still working on functionality. src/mem/cache/base_cache.cc: Temp fix for cpu's use of getPort functionality. CPU's will need to be ported to the new connector objects. Also, all packets have to have data or the delete fails. src/mem/cache/cache.hh: Fix function prototypes so overloading works src/mem/cache/cache_impl.hh: fix functions to match virtual base class src/mem/cache/miss/miss_queue.cc: Packets havve to have data, or delete fails src/python/m5/objects/BaseCache.py: Update for newmem --HG-- extra : convert_revision : 2b6ad1e9d8ae07ace9294cd257e2ccc0024b7fcb
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/base_cache.cc21
-rw-r--r--src/mem/cache/cache.hh6
-rw-r--r--src/mem/cache/cache_impl.hh8
-rw-r--r--src/mem/cache/miss/miss_queue.cc3
4 files changed, 22 insertions, 16 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index c1ed6d3d4..aaaf1bdef 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -101,16 +101,21 @@ BaseCache::CachePort::clearBlocked()
Port*
BaseCache::getPort(const std::string &if_name, int idx)
{
- if(if_name == "cpu_side")
+ if (if_name == "")
{
- if(cpuSidePort != NULL)
- panic("Already have a cpu side for this cache\n");
- cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
+ if(cpuSidePort == NULL)
+ cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
return cpuSidePort;
}
- else if(if_name == "mem_side")
+ if (if_name == "functional")
{
- if(memSidePort != NULL)
+ if(cpuSidePort == NULL)
+ cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
+ return cpuSidePort;
+ }
+ else if (if_name == "mem_side")
+ {
+ if (memSidePort != NULL)
panic("Already have a mem side for this cache\n");
memSidePort = new CachePort(name() + "-mem_side_port", this, false);
return memSidePort;
@@ -121,9 +126,10 @@ BaseCache::getPort(const std::string &if_name, int idx)
void
BaseCache::regStats()
{
- Request temp_req;
+ Request temp_req((Addr) NULL, 4, 0);
Packet::Command temp_cmd = Packet::ReadReq;
Packet temp_pkt(&temp_req, temp_cmd, 0); //@todo FIx command strings so this isn't neccessary
+ temp_pkt.allocate(); //Temp allocate, all need data
using namespace Stats;
@@ -331,4 +337,5 @@ BaseCache::regStats()
.name(name() + ".cache_copies")
.desc("number of cache copies performed")
;
+
}
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 788715e76..1243c9d9e 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -149,11 +149,9 @@ class Cache : public BaseCache
virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
bool isCpuSide);
- virtual Tick doAtomicAccess(Packet *pkt, CachePort *cachePort,
- bool isCpuSide);
+ virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
- virtual void doFunctionalAccess(Packet *pkt, CachePort *cachePort,
- bool isCpuSide);
+ virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
virtual void recvStatusChange(Port::Status status, bool isCpuSide);
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index f1e9c3698..0cb33461b 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -77,7 +77,7 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
template<class TagStore, class Buffering, class Coherence>
Tick
Cache<TagStore,Buffering,Coherence>::
-doAtomicAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
+doAtomicAccess(Packet *pkt, bool isCpuSide)
{
if (isCpuSide)
{
@@ -97,18 +97,18 @@ doAtomicAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
template<class TagStore, class Buffering, class Coherence>
void
Cache<TagStore,Buffering,Coherence>::
-doFunctionalAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
+doFunctionalAccess(Packet *pkt, bool isCpuSide)
{
if (isCpuSide)
{
- probe(pkt, false);
+ probe(pkt, true);
}
else
{
if (pkt->isResponse())
handleResponse(pkt);
else
- snoopProbe(pkt, false);
+ snoopProbe(pkt, true);
}
}
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index 99ebab017..da0448ad3 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -58,9 +58,10 @@ MissQueue::MissQueue(int numMSHRs, int numTargets, int write_buffers,
void
MissQueue::regStats(const string &name)
{
- Request temp_req;
+ Request temp_req((Addr) NULL, 4, 0);
Packet::Command temp_cmd = Packet::ReadReq;
Packet temp_pkt(&temp_req, temp_cmd, 0); //@todo FIx command strings so this isn't neccessary
+ temp_pkt.allocate();
using namespace Stats;