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authorLisa Hsu <Lisa.Hsu@amd.com>2010-01-12 10:53:02 -0800
committerLisa Hsu <Lisa.Hsu@amd.com>2010-01-12 10:53:02 -0800
commit8b4e8690b73f61ae0bb2cb052ec56f58d1d531e2 (patch)
tree34001c05d1ff8c1a6d30a0356ff2623c49e16a0b /src/mem/cache
parent9f635484784a9a523fc356df9e55922660d13d8f (diff)
downloadgem5-8b4e8690b73f61ae0bb2cb052ec56f58d1d531e2.tar.xz
cache: make tags->insertBlock() and tags->accessBlock() context aware so that the cache can make context-specific decisions within their various tag policy implementations.
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/cache_impl.hh9
-rw-r--r--src/mem/cache/tags/fa_lru.cc4
-rw-r--r--src/mem/cache/tags/fa_lru.hh4
-rw-r--r--src/mem/cache/tags/iic.cc4
-rw-r--r--src/mem/cache/tags/iic.hh4
-rw-r--r--src/mem/cache/tags/lru.cc4
-rw-r--r--src/mem/cache/tags/lru.hh4
7 files changed, 18 insertions, 15 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 429928c79..2397a17c5 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -266,7 +266,8 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
return false;
}
- blk = tags->accessBlock(pkt->getAddr(), lat);
+ int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
+ blk = tags->accessBlock(pkt->getAddr(), lat, id);
DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(),
pkt->req->isInstFetch() ? " (ifetch)" : "",
@@ -299,7 +300,8 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
incMissCount(pkt);
return false;
}
- tags->insertBlock(pkt->getAddr(), blk);
+ int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
+ tags->insertBlock(pkt->getAddr(), blk, id);
blk->status = BlkValid | BlkReadable;
}
std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
@@ -976,7 +978,8 @@ Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk,
tempBlock->tag = tags->extractTag(addr);
DPRINTF(Cache, "using temp block for %x\n", addr);
} else {
- tags->insertBlock(addr, blk);
+ int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
+ tags->insertBlock(pkt->getAddr(), blk, id);
}
} else {
// existing block... probably an upgrade
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index 122e6e14b..808f9e25a 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -154,7 +154,7 @@ FALRU::invalidateBlk(FALRU::BlkType *blk)
}
FALRUBlk*
-FALRU::accessBlock(Addr addr, int &lat, int *inCache)
+FALRU::accessBlock(Addr addr, int &lat, int context_src, int *inCache)
{
accesses++;
int tmp_in_cache = 0;
@@ -228,7 +228,7 @@ FALRU::findVictim(Addr addr, PacketList &writebacks)
}
void
-FALRU::insertBlock(Addr addr, FALRU::BlkType *blk)
+FALRU::insertBlock(Addr addr, FALRU::BlkType *blk, int context_src)
{
}
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index 4e6bccc1d..b20d25d2b 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -182,7 +182,7 @@ public:
* @param inCache The FALRUBlk::inCache flags.
* @return Pointer to the cache block.
*/
- FALRUBlk* accessBlock(Addr addr, int &lat, int *inCache = 0);
+ FALRUBlk* accessBlock(Addr addr, int &lat, int context_src, int *inCache = 0);
/**
* Find the block in the cache, do not update the replacement data.
@@ -200,7 +200,7 @@ public:
*/
FALRUBlk* findVictim(Addr addr, PacketList & writebacks);
- void insertBlock(Addr addr, BlkType *blk);
+ void insertBlock(Addr addr, BlkType *blk, int context_src);
/**
* Return the hit latency of this cache.
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index b9ba5256b..a8ef4e6fb 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -219,7 +219,7 @@ IIC::regStats(const string &name)
IICTag*
-IIC::accessBlock(Addr addr, int &lat)
+IIC::accessBlock(Addr addr, int &lat, int context_src)
{
Addr tag = extractTag(addr);
unsigned set = hash(addr);
@@ -338,7 +338,7 @@ IIC::findVictim(Addr addr, PacketList &writebacks)
}
void
-IIC::insertBlock(Addr addr, BlkType* blk)
+IIC::insertBlock(Addr addr, BlkType* blk, int context_src)
{
}
diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh
index 994f7b8f7..c96cdaf3e 100644
--- a/src/mem/cache/tags/iic.hh
+++ b/src/mem/cache/tags/iic.hh
@@ -422,7 +422,7 @@ class IIC : public BaseTags
* @param lat The access latency.
* @return A pointer to the block found, if any.
*/
- IICTag* accessBlock(Addr addr, int &lat);
+ IICTag* accessBlock(Addr addr, int &lat, int context_src);
/**
* Find the block, do not update the replacement data.
@@ -440,7 +440,7 @@ class IIC : public BaseTags
*/
IICTag* findVictim(Addr addr, PacketList &writebacks);
- void insertBlock(Addr addr, BlkType *blk);
+ void insertBlock(Addr addr, BlkType *blk, int context_src);
/**
* Called at end of simulation to complete average block reference stats.
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index 9371f193a..81d82c231 100644
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -150,7 +150,7 @@ LRU::~LRU()
}
LRUBlk*
-LRU::accessBlock(Addr addr, int &lat)
+LRU::accessBlock(Addr addr, int &lat, int context_src)
{
Addr tag = extractTag(addr);
unsigned set = extractSet(addr);
@@ -200,7 +200,7 @@ LRU::findVictim(Addr addr, PacketList &writebacks)
}
void
-LRU::insertBlock(Addr addr, LRU::BlkType *blk)
+LRU::insertBlock(Addr addr, LRU::BlkType *blk, int context_src)
{
if (!blk->isTouched) {
tagsInUse++;
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index 2874d8f1f..ecd6e861f 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -172,7 +172,7 @@ public:
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
- LRUBlk* accessBlock(Addr addr, int &lat);
+ LRUBlk* accessBlock(Addr addr, int &lat, int context_src);
/**
* Finds the given address in the cache, do not update replacement data.
@@ -197,7 +197,7 @@ public:
* @param addr The address to update.
* @param blk The block to update.
*/
- void insertBlock(Addr addr, BlkType *blk);
+ void insertBlock(Addr addr, BlkType *blk, int context_src);
/**
* Generate the tag from the given address.