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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-08-01 22:50:14 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-08-01 22:50:14 -0700 |
| commit | a13a706a207296b40dbe43576fad423cf5f4679a (patch) | |
| tree | 119bd1bd09542130d603c8f30c0494313180753a /src/mem/cache | |
| parent | 1c2800465480993040e3058ef94ce30efbe982ec (diff) | |
| download | gem5-a13a706a207296b40dbe43576fad423cf5f4679a.tar.xz | |
Fix setting of INST_FETCH flag for O3 CPU.
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 0940893bc..80b7c545c 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -268,8 +268,9 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk, blk = tags->accessBlock(pkt->getAddr(), lat); - DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), pkt->getAddr(), - (blk) ? "hit" : "miss"); + DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(), + pkt->req->isInstFetch() ? " (ifetch)" : "", + pkt->getAddr(), (blk) ? "hit" : "miss"); if (blk != NULL) { |