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authorAndreas Hansson <andreas.hansson@arm.com>2016-02-24 04:16:57 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2016-02-24 04:16:57 -0500
commit7958f34797857fecf803fa4a2fcd018a8fffb640 (patch)
treedbf93b72ae03dd49a915c81388d522b8cb8d75d0 /src/mem/cache
parent496a8c6c924b2b970eafa941b2617aca789ebe3c (diff)
downloadgem5-7958f34797857fecf803fa4a2fcd018a8fffb640.tar.xz
mem: Ensure that InvalidateReq is not forwarded as ReadExReq
This patch fixes an issue where an InvalidationReq only traversed one level of the cache hierarchy, and was subsequently turned into a ReadExReq due to it needing writable, and the command not being checked for explicitly.
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/cache.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index e9b909646..724ccc7d6 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -966,7 +966,8 @@ Cache::getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk,
// where the determination the StoreCond fails is delayed due to
// all caches not being on the same local bus.
cmd = MemCmd::SCUpgradeFailReq;
- } else if (cpu_pkt->cmd == MemCmd::WriteLineReq) {
+ } else if (cpu_pkt->cmd == MemCmd::WriteLineReq ||
+ cpu_pkt->cmd == MemCmd::InvalidateReq) {
// forward as invalidate to all other caches, this gives us
// the line in Exclusive state, and invalidates all other
// copies