merge

6 files changed, 17 insertions, 33 deletions

diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index bdef07cb4..5ded05400 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -68,8 +68,6 @@ class BaseCache(MemObject):
          "Latency of the prefetcher")
     prefetch_policy = Param.Prefetch('none',
          "Type of prefetcher to use")
-    prefetch_cache_check_push = Param.Bool(True,
-         "Check if in cache on push or pop of prefetch queue")
     prefetch_use_cpu_id = Param.Bool(True,
          "Use the CPU ID to separate calculations of prefetches")
     prefetch_data_accesses_only = Param.Bool(False,
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 24f993383..c245fecd2 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -379,7 +379,7 @@ class BaseCache : public MemObject
     }
 
 
-    Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); }
+    Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
 
 
     const Range<Addr> &getAddrRange() const { return addrRange; }
diff --git a/src/mem/cache/builder.cc b/src/mem/cache/builder.cc
index 599353b88..bd9eb9acc 100644
--- a/src/mem/cache/builder.cc
+++ b/src/mem/cache/builder.cc
@@ -33,9 +33,10 @@
  * @file
  * Simobject instatiation of caches.
  */
+#include <list>
 #include <vector>
 
-// Must be included first to determine which caches we want
+#include "config/the_isa.hh"
 #include "enums/Prefetch.hh"
 #include "mem/config/cache.hh"
 #include "mem/cache/base.hh"
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 80b7c545c..429928c79 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -449,7 +449,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
     } else {
         // miss
 
-        Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
+        Addr blk_addr = blockAlign(pkt->getAddr());
         MSHR *mshr = mshrQueue.findMatch(blk_addr);
 
         if (mshr) {
@@ -692,7 +692,7 @@ Cache<TagStore>::functionalAccess(PacketPtr pkt,
                                   CachePort *incomingPort,
                                   CachePort *otherSidePort)
 {
-    Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
+    Addr blk_addr = blockAlign(pkt->getAddr());
     BlkType *blk = tags->findBlock(pkt->getAddr());
 
     pkt->pushLabel(name());
@@ -1162,7 +1162,7 @@ Cache<TagStore>::snoopTiming(PacketPtr pkt)
 
     BlkType *blk = tags->findBlock(pkt->getAddr());
 
-    Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
+    Addr blk_addr = blockAlign(pkt->getAddr());
     MSHR *mshr = mshrQueue.findMatch(blk_addr);
 
     // Let the MSHR itself track the snoop and decide whether we want
@@ -1301,11 +1301,14 @@ Cache<TagStore>::getNextMSHR()
         // If we have a miss queue slot, we can try a prefetch
         PacketPtr pkt = prefetcher->getPacket();
         if (pkt) {
-            // Update statistic on number of prefetches issued
-            // (hwpf_mshr_misses)
-            mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
-            // Don't request bus, since we already have it
-            return allocateMissBuffer(pkt, curTick, false);
+            Addr pf_addr = blockAlign(pkt->getAddr());
+            if (!tags->findBlock(pf_addr) && !mshrQueue.findMatch(pf_addr)) {
+                // Update statistic on number of prefetches issued
+                // (hwpf_mshr_misses)
+                mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
+                // Don't request bus, since we already have it
+                return allocateMissBuffer(pkt, curTick, false);
+            }
         }
     }
 
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index f20a306cb..ad7a0c882 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -33,17 +33,18 @@
  * Hardware Prefetcher Definition.
  */
 
+#include <list>
+
 #include "arch/isa_traits.hh"
 #include "base/trace.hh"
+#include "config/the_isa.hh"
 #include "mem/cache/base.hh"
 #include "mem/cache/prefetch/base.hh"
 #include "mem/request.hh"
-#include <list>
 
 BasePrefetcher::BasePrefetcher(const BaseCacheParams *p)
     : size(p->prefetcher_size), pageStop(!p->prefetch_past_page),
       serialSquash(p->prefetch_serial_squash),
-      cacheCheckPush(p->prefetch_cache_check_push),
       onlyData(p->prefetch_data_accesses_only)
 {
 }
@@ -141,9 +142,6 @@ BasePrefetcher::getPacket()
     do {
         pkt = *pf.begin();
         pf.pop_front();
-        if (!cacheCheckPush) {
-            keep_trying = cache->inCache(pkt->getAddr());
-        }
 
         if (keep_trying) {
             DPRINTF(HWPrefetch, "addr 0x%x in cache, skipping\n",
@@ -224,18 +222,6 @@ BasePrefetcher::notify(PacketPtr &pkt, Tick time)
                     "inserting into prefetch queue with delay %d time %d\n",
                     addr, *delayIter, time);
 
-            // Check if it is already in the cache
-            if (cacheCheckPush && cache->inCache(addr)) {
-                DPRINTF(HWPrefetch, "Prefetch addr already in cache\n");
-                continue;
-            }
-
-            // Check if it is already in the miss_queue
-            if (cache->inMissQueue(addr)) {
-                DPRINTF(HWPrefetch, "Prefetch addr already in miss queue\n");
-                continue;
-            }
-
             // Check if it is already in the pf buffer
             if (inPrefetch(addr) != pf.end()) {
                 pfBufferHit++;
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index b5f33a455..e3c0cbf16 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -68,10 +68,6 @@ class BasePrefetcher
     /** Do we remove prefetches with later times than a new miss.*/
     bool serialSquash;
 
-    /** Do we check if it is in the cache when inserting into buffer,
-        or removing.*/
-    bool cacheCheckPush;
-
     /** Do we prefetch on only data reads, or on inst reads as well. */
     bool onlyData;