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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-03-11 23:05:26 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-03-11 23:05:26 -0700 |
| commit | 758bfe4eb57e5b7aada4c974830532ec067a5bda (patch) | |
| tree | f5936dec94f86059735ed692992e77def2ad7033 /src/mem/cache | |
| parent | 61ff48a1f834b7335c2ae615a1f855995cfab335 (diff) | |
| download | gem5-758bfe4eb57e5b7aada4c974830532ec067a5bda.tar.xz | |
cache: set dirty bit on swaps (oops!)
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 618e00569..a78fd3637 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -149,8 +149,10 @@ Cache<TagStore>::cmpAndSwap(BlkType *blk, PacketPtr pkt) panic("Invalid size for conditional read/write\n"); } - if (overwrite_mem) + if (overwrite_mem) { std::memcpy(blk_data, &overwrite_val, pkt->getSize()); + blk->status |= BlkDirty; + } } |