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authorSteve Reinhardt <stever@eecs.umich.edu>2007-05-27 21:34:37 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2007-05-27 21:34:37 -0700
commit075f4b108a325e9cf2b903cd17fdbcac7598b6b0 (patch)
tree1d92cb303f6b0f7547ed0119f757fb7b30d2833b /src/mem/cache
parent6a48f6b67d41b03e04aaba8e5fbe4e20059a9b9f (diff)
parent35147170f91ccbc73d3e75440a5301f758e54dfc (diff)
downloadgem5-075f4b108a325e9cf2b903cd17fdbcac7598b6b0.tar.xz
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : fba7efd444e1ca9738385dd4662a33feab357e79
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/BaseCache.py91
-rw-r--r--src/mem/cache/SConscript2
-rw-r--r--src/mem/cache/coherence/CoherenceProtocol.py8
-rw-r--r--src/mem/cache/coherence/SConscript2
-rw-r--r--src/mem/cache/tags/Repl.py11
-rw-r--r--src/mem/cache/tags/SConscript1
6 files changed, 115 insertions, 0 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
new file mode 100644
index 000000000..4b98f6b30
--- /dev/null
+++ b/src/mem/cache/BaseCache.py
@@ -0,0 +1,91 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+from MemObject import MemObject
+
+class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
+
+class BaseCache(MemObject):
+ type = 'BaseCache'
+ adaptive_compression = Param.Bool(False,
+ "Use an adaptive compression scheme")
+ assoc = Param.Int("associativity")
+ block_size = Param.Int("block size in bytes")
+ latency = Param.Latency("Latency")
+ compressed_bus = Param.Bool(False,
+ "This cache connects to a compressed memory")
+ compression_latency = Param.Latency('0ns',
+ "Latency in cycles of compression algorithm")
+ hash_delay = Param.Int(1, "time in cycles of hash access")
+ lifo = Param.Bool(False,
+ "whether this NIC partition should use LIFO repl. policy")
+ max_miss_count = Param.Counter(0,
+ "number of misses to handle before calling exit")
+ mshrs = Param.Int("number of MSHRs (max outstanding requests)")
+ prioritizeRequests = Param.Bool(False,
+ "always service demand misses first")
+ protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
+ repl = Param.Repl(NULL, "replacement policy")
+ size = Param.MemorySize("capacity in bytes")
+ split = Param.Bool(False, "whether or not this cache is split")
+ split_size = Param.Int(0,
+ "How many ways of the cache belong to CPU/LRU partition")
+ store_compressed = Param.Bool(False,
+ "Store compressed data in the cache")
+ subblock_size = Param.Int(0,
+ "Size of subblock in IIC used for compression")
+ tgts_per_mshr = Param.Int("max number of accesses per MSHR")
+ trace_addr = Param.Addr(0, "address to trace")
+ two_queue = Param.Bool(False,
+ "whether the lifo should have two queue replacement")
+ write_buffers = Param.Int(8, "number of write buffers")
+ prefetch_miss = Param.Bool(False,
+ "wheter you are using the hardware prefetcher from Miss stream")
+ prefetch_access = Param.Bool(False,
+ "wheter you are using the hardware prefetcher from Access stream")
+ prefetcher_size = Param.Int(100,
+ "Number of entries in the harware prefetch queue")
+ prefetch_past_page = Param.Bool(False,
+ "Allow prefetches to cross virtual page boundaries")
+ prefetch_serial_squash = Param.Bool(False,
+ "Squash prefetches with a later time on a subsequent miss")
+ prefetch_degree = Param.Int(1,
+ "Degree of the prefetch depth")
+ prefetch_latency = Param.Tick(10,
+ "Latency of the prefetcher")
+ prefetch_policy = Param.Prefetch('none',
+ "Type of prefetcher to use")
+ prefetch_cache_check_push = Param.Bool(True,
+ "Check if in cash on push or pop of prefetch queue")
+ prefetch_use_cpu_id = Param.Bool(True,
+ "Use the CPU ID to seperate calculations of prefetches")
+ prefetch_data_accesses_only = Param.Bool(False,
+ "Only prefetch on data not on instruction accesses")
+ cpu_side = Port("Port on side closer to CPU")
+ mem_side = Port("Port on side closer to MEM")
diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index 7150719ad..546e037bd 100644
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -30,6 +30,8 @@
Import('*')
+SimObject('BaseCache.py')
+
Source('base_cache.cc')
Source('cache.cc')
Source('cache_builder.cc')
diff --git a/src/mem/cache/coherence/CoherenceProtocol.py b/src/mem/cache/coherence/CoherenceProtocol.py
new file mode 100644
index 000000000..82adb6862
--- /dev/null
+++ b/src/mem/cache/coherence/CoherenceProtocol.py
@@ -0,0 +1,8 @@
+from m5.SimObject import SimObject
+from m5.params import *
+class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi']
+
+class CoherenceProtocol(SimObject):
+ type = 'CoherenceProtocol'
+ do_upgrades = Param.Bool(True, "use upgrade transactions?")
+ protocol = Param.Coherence("name of coherence protocol")
diff --git a/src/mem/cache/coherence/SConscript b/src/mem/cache/coherence/SConscript
index 7b94f73e1..91720b20e 100644
--- a/src/mem/cache/coherence/SConscript
+++ b/src/mem/cache/coherence/SConscript
@@ -30,5 +30,7 @@
Import('*')
+SimObject('CoherenceProtocol.py')
+
Source('coherence_protocol.cc')
diff --git a/src/mem/cache/tags/Repl.py b/src/mem/cache/tags/Repl.py
new file mode 100644
index 000000000..b76aa1d6e
--- /dev/null
+++ b/src/mem/cache/tags/Repl.py
@@ -0,0 +1,11 @@
+from m5.SimObject import SimObject
+from m5.params import *
+class Repl(SimObject):
+ type = 'Repl'
+ abstract = True
+
+class GenRepl(Repl):
+ type = 'GenRepl'
+ fresh_res = Param.Int("Fresh pool residency time")
+ num_pools = Param.Int("Number of priority pools")
+ pool_res = Param.Int("Pool residency time")
diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index baf71f687..3fcaec4fa 100644
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -38,5 +38,6 @@ Source('split.cc')
Source('split_lifo.cc')
Source('split_lru.cc')
+SimObject('Repl.py')
Source('repl/gen.cc')
Source('repl/repl.cc')