mem-cache: Make invalidate a common function between tag classes

invalidate was defined as a separate function in the base associative
and fully-associative tags classes although both functions should
implement identical functionality. This patch moves the invalidate
function in the base tags class.

Change-Id: I206ee969b00ab9e05873c6d87531474fcd712907
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8286
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

7 files changed, 52 insertions, 38 deletions

diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 44691c122..66f05c884 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2016 ARM Limited
+ * Copyright (c) 2012-2017 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -164,12 +164,9 @@ class CacheBlk
   public:
 
     CacheBlk()
-        : task_id(ContextSwitchTaskId::Unknown),
-          tag(0), data(0), status(0), whenReady(0),
-          set(-1), way(-1), isTouched(false), refCount(0),
-          srcMasterId(Request::invldMasterId),
-          tickInserted(0)
-    {}
+    {
+        invalidate();
+    }
 
     CacheBlk(const CacheBlk&) = delete;
     CacheBlk& operator=(const CacheBlk&) = delete;
@@ -210,8 +207,14 @@ class CacheBlk
      */
     void invalidate()
     {
+        tag = MaxAddr;
+        task_id = ContextSwitchTaskId::Unknown;
         status = 0;
+        whenReady = MaxTick;
         isTouched = false;
+        refCount = 0;
+        srcMasterId = Request::invldMasterId;
+        tickInserted = MaxTick;
         lockList.clear();
     }
 
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 9714d9aa2..dfd8aeb62 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2014,2016 ARM Limited
+ * Copyright (c) 2012-2014,2016-2017 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -236,7 +236,18 @@ class BaseTags : public ClockedObject
         return -1;
     }
 
-    virtual void invalidate(CacheBlk *blk) = 0;
+    /**
+     * This function updates the tags when a block is invalidated but
+     * does not invalidate the block itself.
+     * @param blk The block to invalidate.
+     */
+    virtual void invalidate(CacheBlk *blk)
+    {
+        assert(blk);
+        assert(blk->isValid());
+        tagsInUse--;
+        occupancies[blk->srcMasterId]--;
+    }
 
     virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) = 0;
 
diff --git a/src/mem/cache/tags/base_set_assoc.hh b/src/mem/cache/tags/base_set_assoc.hh
index 44f68d5fc..835b0cfd4 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2014 ARM Limited
+ * Copyright (c) 2012-2014,2017 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -72,7 +72,6 @@
  * BlkType* accessBlock();
  * BlkType* findVictim();
  * void insertBlock();
- * void invalidate();
  */
 class BaseSetAssoc : public BaseTags
 {
@@ -134,22 +133,6 @@ public:
     CacheBlk *findBlockBySetAndWay(int set, int way) const override;
 
     /**
-     * Invalidate the given block.
-     * @param blk The block to invalidate.
-     */
-    void invalidate(CacheBlk *blk) override
-    {
-        assert(blk);
-        assert(blk->isValid());
-        tagsInUse--;
-        assert(blk->srcMasterId < cache->system->maxMasters());
-        occupancies[blk->srcMasterId]--;
-        blk->srcMasterId = Request::invldMasterId;
-        blk->task_id = ContextSwitchTaskId::Unknown;
-        blk->tickInserted = curTick();
-    }
-
-    /**
      * Access block and update replacement data. May not succeed, in which case
      * nullptr is returned. This has all the implications of a cache
      * access and should only be used as such. Returns the access latency as a
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index 1ee34b7d8..d40398975 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013,2016 ARM Limited
+ * Copyright (c) 2013,2016-2017 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -163,8 +163,8 @@ FALRU::hashLookup(Addr addr) const
 void
 FALRU::invalidate(CacheBlk *blk)
 {
-    assert(blk);
-    tagsInUse--;
+    // TODO: We need to move the block to the tail to make it the next victim
+    BaseTags::invalidate(blk);
 }
 
 CacheBlk*
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index d38b94ed3..530b07ad7 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -72,7 +72,7 @@ class LRU : public BaseSetAssoc
     CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat);
     CacheBlk* findVictim(Addr addr);
     void insertBlock(PacketPtr pkt, BlkType *blk);
-    void invalidate(CacheBlk *blk);
+    void invalidate(CacheBlk *blk) override;
 };
 
 #endif // __MEM_CACHE_TAGS_LRU_HH__
diff --git a/src/mem/cache/tags/random_repl.cc b/src/mem/cache/tags/random_repl.cc
index ab51f6407..c06b12096 100644
--- a/src/mem/cache/tags/random_repl.cc
+++ b/src/mem/cache/tags/random_repl.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2014 The Regents of The University of Michigan
  * Copyright (c) 2016 ARM Limited
  * All rights reserved.
@@ -86,12 +98,6 @@ RandomRepl::insertBlock(PacketPtr pkt, BlkType *blk)
     BaseSetAssoc::insertBlock(pkt, blk);
 }
 
-void
-RandomRepl::invalidate(CacheBlk *blk)
-{
-    BaseSetAssoc::invalidate(blk);
-}
-
 RandomRepl*
 RandomReplParams::create()
 {
diff --git a/src/mem/cache/tags/random_repl.hh b/src/mem/cache/tags/random_repl.hh
index 8f08a7034..71b2f5ce6 100644
--- a/src/mem/cache/tags/random_repl.hh
+++ b/src/mem/cache/tags/random_repl.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2014 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -61,7 +73,6 @@ class RandomRepl : public BaseSetAssoc
     CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat);
     CacheBlk* findVictim(Addr addr);
     void insertBlock(PacketPtr pkt, BlkType *blk);
-    void invalidate(CacheBlk *blk);
 };
 
 #endif // __MEM_CACHE_TAGS_RANDOM_REPL_HH__