DMA: Add IOCache and fix bus bridge to optionally only send requests one

way so a cache can handle partial block requests for i/o devices.

--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964

6 files changed, 42 insertions, 15 deletions

diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index 2bf44cdf9..f6d42b1ef 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -81,4 +81,8 @@ class BaseCache(MemObject):
          "Only prefetch on data not on instruction accesses")
     cpu_side = Port("Port on side closer to CPU")
     mem_side = Port("Port on side closer to MEM")
+    cpu_side_filter_ranges = VectorParam.AddrRange([],
+            "What addresses shouldn't be passed through the side of the bridge")
+    mem_side_filter_ranges = VectorParam.AddrRange([],
+            "What addresses shouldn't be passed through the side of the bridge")
     addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes")
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index b44468486..0c8b02cb3 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -40,9 +40,10 @@
 
 using namespace std;
 
-BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache)
+BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
+        std::vector<Range<Addr> > filter_ranges)
     : SimpleTimingPort(_name, _cache), cache(_cache), otherPort(NULL),
-      blocked(false), mustSendRetry(false)
+      blocked(false), mustSendRetry(false), filterRanges(filter_ranges)
 {
 }
 
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 719ab0245..6a4eec43e 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -98,7 +98,8 @@ class BaseCache : public MemObject
         BaseCache *cache;
 
       protected:
-        CachePort(const std::string &_name, BaseCache *_cache);
+        CachePort(const std::string &_name, BaseCache *_cache,
+                std::vector<Range<Addr> > filter_ranges);
 
         virtual void recvStatusChange(Status status);
 
@@ -124,6 +125,9 @@ class BaseCache : public MemObject
 
         bool mustSendRetry;
 
+        /** filter ranges */
+        std::vector<Range<Addr> > filterRanges;
+
         void requestBus(RequestCause cause, Tick time)
         {
             DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
@@ -367,15 +371,21 @@ class BaseCache : public MemObject
          */
         Counter maxMisses;
 
+        std::vector<Range<Addr> > cpuSideFilterRanges;
+        std::vector<Range<Addr> > memSideFilterRanges;
         /**
          * Construct an instance of this parameter class.
          */
         Params(int _hitLatency, int _blkSize,
                int _numMSHRs, int _numTargets, int _numWriteBuffers,
-               Counter _maxMisses)
+               Counter _maxMisses,
+               std::vector<Range<Addr> > cpu_side_filter_ranges,
+               std::vector<Range<Addr> > mem_side_filter_ranges)
             : hitLatency(_hitLatency), blkSize(_blkSize),
               numMSHRs(_numMSHRs), numTargets(_numTargets),
-              numWriteBuffers(_numWriteBuffers), maxMisses(_maxMisses)
+              numWriteBuffers(_numWriteBuffers), maxMisses(_maxMisses),
+              cpuSideFilterRanges(cpu_side_filter_ranges),
+              memSideFilterRanges(mem_side_filter_ranges)
         {
         }
     };
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 57028a05e..821fa9702 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -72,7 +72,8 @@ class Cache : public BaseCache
     {
       public:
         CpuSidePort(const std::string &_name,
-                    Cache<TagStore> *_cache);
+                    Cache<TagStore> *_cache,
+                    std::vector<Range<Addr> > filterRanges);
 
         // BaseCache::CachePort just has a BaseCache *; this function
         // lets us get back the type info we lost when we stored the
@@ -95,7 +96,8 @@ class Cache : public BaseCache
     {
       public:
         MemSidePort(const std::string &_name,
-                    Cache<TagStore> *_cache);
+                    Cache<TagStore> *_cache,
+                    std::vector<Range<Addr> > filterRanges);
 
         // BaseCache::CachePort just has a BaseCache *; this function
         // lets us get back the type info we lost when we stored the
diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc
index 4c9592a1b..0f8b52af2 100644
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@ -241,7 +241,8 @@ BaseCacheParams::create()
     // Build BaseCache param object
     BaseCache::Params base_params(latency, block_size,
                                   mshrs, tgts_per_mshr, write_buffers,
-                                  max_miss_count);
+                                  max_miss_count, cpu_side_filter_ranges,
+                                  mem_side_filter_ranges);
 
     //Warnings about prefetcher policy
     if (prefetch_policy == Enums::none) {
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index d144266ed..402e34db2 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -39,6 +39,7 @@
 
 #include "sim/host.hh"
 #include "base/misc.hh"
+#include "base/range_ops.hh"
 
 #include "mem/cache/cache.hh"
 #include "mem/cache/cache_blk.hh"
@@ -61,8 +62,10 @@ Cache<TagStore>::Cache(const std::string &_name,
     tempBlock = new BlkType();
     tempBlock->data = new uint8_t[blkSize];
 
-    cpuSidePort = new CpuSidePort(_name + "-cpu_side_port", this);
-    memSidePort = new MemSidePort(_name + "-mem_side_port", this);
+    cpuSidePort = new CpuSidePort(_name + "-cpu_side_port", this,
+            params.baseParams.cpuSideFilterRanges);
+    memSidePort = new MemSidePort(_name + "-mem_side_port", this,
+            params.baseParams.memSideFilterRanges);
     cpuSidePort->setOtherPort(memSidePort);
     memSidePort->setOtherPort(cpuSidePort);
 
@@ -88,7 +91,8 @@ Cache<TagStore>::getPort(const std::string &if_name, int idx)
     } else if (if_name == "mem_side") {
         return memSidePort;
     } else if (if_name == "functional") {
-        return new CpuSidePort(name() + "-cpu_side_funcport", this);
+        return new CpuSidePort(name() + "-cpu_side_funcport", this,
+                std::vector<Range<Addr> >());
     } else {
         panic("Port name %s unrecognized\n", if_name);
     }
@@ -1221,6 +1225,7 @@ getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
     // CPU side port doesn't snoop; it's a target only.
     bool dummy;
     otherPort->getPeerAddressRanges(resp, dummy);
+    FilterRangeList(filterRanges, resp);
     snoop = false;
 }
 
@@ -1262,8 +1267,9 @@ Cache<TagStore>::CpuSidePort::recvFunctional(PacketPtr pkt)
 template<class TagStore>
 Cache<TagStore>::
 CpuSidePort::CpuSidePort(const std::string &_name,
-                         Cache<TagStore> *_cache)
-    : BaseCache::CachePort(_name, _cache)
+                         Cache<TagStore> *_cache, std::vector<Range<Addr> >
+                         filterRanges)
+    : BaseCache::CachePort(_name, _cache, filterRanges)
 {
 }
 
@@ -1279,6 +1285,8 @@ Cache<TagStore>::MemSidePort::
 getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
 {
     otherPort->getPeerAddressRanges(resp, snoop);
+    FilterRangeList(filterRanges, resp);
+
     // Memory-side port always snoops, so unconditionally set flag for
     // caller.
     snoop = true;
@@ -1416,8 +1424,9 @@ Cache<TagStore>::MemSidePort::processSendEvent()
 
 template<class TagStore>
 Cache<TagStore>::
-MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache)
-    : BaseCache::CachePort(_name, _cache)
+MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
+        std::vector<Range<Addr> > filterRanges)
+    : BaseCache::CachePort(_name, _cache, filterRanges)
 {
     // override default send event from SimpleTimingPort
     delete sendEvent;