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authorAndreas Hansson <andreas.hansson@arm.com>2015-10-12 04:07:59 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-10-12 04:07:59 -0400
commit22c04190c607b9360d9a23548f8a54e83cf0e74a (patch)
tree576135962e3c9c725157b461c8009b05933bba2b /src/mem/cache
parent735c4a87665119a33443cf8d191d329c66191c6e (diff)
downloadgem5-22c04190c607b9360d9a23548f8a54e83cf0e74a.tar.xz
misc: Remove redundant compiler-specific defines
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions.
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/cache.hh8
-rw-r--r--src/mem/cache/mshr_queue.hh2
-rw-r--r--src/mem/cache/prefetch/stride.hh5
-rw-r--r--src/mem/cache/tags/base_set_assoc.hh2
-rw-r--r--src/mem/cache/tags/fa_lru.hh6
5 files changed, 12 insertions, 11 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 26c9637f0..0ee0696d8 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -435,8 +435,8 @@ class Cache : public BaseCache
/** serialize the state of the caches
* We currently don't support checkpointing cache state, so this panics.
*/
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
/**
@@ -455,7 +455,7 @@ class CacheBlkVisitorWrapper : public CacheBlkVisitor
CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor)
: cache(_cache), visitor(_visitor) {}
- bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE {
+ bool operator()(CacheBlk &blk) override {
return (cache.*visitor)(blk);
}
@@ -477,7 +477,7 @@ class CacheBlkIsDirtyVisitor : public CacheBlkVisitor
CacheBlkIsDirtyVisitor()
: _isDirty(false) {}
- bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE {
+ bool operator()(CacheBlk &blk) override {
if (blk.isDirty()) {
_isDirty = true;
return false;
diff --git a/src/mem/cache/mshr_queue.hh b/src/mem/cache/mshr_queue.hh
index 308d371fe..eebfed827 100644
--- a/src/mem/cache/mshr_queue.hh
+++ b/src/mem/cache/mshr_queue.hh
@@ -255,7 +255,7 @@ class MSHRQueue : public Drainable
return readyList.empty() ? MaxTick : readyList.front()->readyTime;
}
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
};
#endif //__MEM_CACHE_MSHR_QUEUE_HH__
diff --git a/src/mem/cache/prefetch/stride.hh b/src/mem/cache/prefetch/stride.hh
index 2798c823f..af17252d8 100644
--- a/src/mem/cache/prefetch/stride.hh
+++ b/src/mem/cache/prefetch/stride.hh
@@ -48,7 +48,8 @@
#ifndef __MEM_CACHE_PREFETCH_STRIDE_HH__
#define __MEM_CACHE_PREFETCH_STRIDE_HH__
-#include "base/hashmap.hh"
+#include <unordered_map>
+
#include "mem/cache/prefetch/queued.hh"
#include "params/StridePrefetcher.hh"
@@ -99,7 +100,7 @@ class StridePrefetcher : public QueuedPrefetcher
const int pcTableAssoc;
const int pcTableSets;
const std::string _name;
- m5::hash_map<int, StrideEntry**> entries;
+ std::unordered_map<int, StrideEntry**> entries;
StrideEntry** allocateNewContext(int context);
};
diff --git a/src/mem/cache/tags/base_set_assoc.hh b/src/mem/cache/tags/base_set_assoc.hh
index 9fe23ea91..e415603d9 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -407,7 +407,7 @@ public:
*
* \param visitor Visitor to call on each block.
*/
- void forEachBlk(CacheBlkVisitor &visitor) M5_ATTR_OVERRIDE {
+ void forEachBlk(CacheBlkVisitor &visitor) override {
for (unsigned i = 0; i < numSets * assoc; ++i) {
if (!visitor(blks[i]))
return;
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index def4c9b2c..1728ee48a 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -49,8 +49,8 @@
#define __MEM_CACHE_TAGS_FA_LRU_HH__
#include <list>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "mem/cache/tags/base.hh"
#include "mem/cache/blk.hh"
#include "mem/packet.hh"
@@ -109,7 +109,7 @@ class FALRU : public BaseTags
FALRUBlk *tail;
/** Hash table type mapping addresses to cache block pointers. */
- typedef m5::hash_map<Addr, FALRUBlk *, m5::hash<Addr> > hash_t;
+ typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t;
/** Iterator into the address hash table. */
typedef hash_t::const_iterator tagIterator;
@@ -322,7 +322,7 @@ public:
*
* \param visitor Visitor to call on each block.
*/
- void forEachBlk(CacheBlkVisitor &visitor) M5_ATTR_OVERRIDE {
+ void forEachBlk(CacheBlkVisitor &visitor) override {
for (int i = 0; i < numBlocks; i++) {
if (!visitor(blks[i]))
return;