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| author | Ali Jafri <ali.jafri@arm.com> | 2015-11-06 03:26:37 -0500 |
|---|---|---|
| committer | Ali Jafri <ali.jafri@arm.com> | 2015-11-06 03:26:37 -0500 |
| commit | 52c8ae5187cb6ba8d15a8de6526f56defe541f5b (patch) | |
| tree | 640bbc8a9d75c731939354a716cd734acad8f909 /src/mem/cache | |
| parent | 6b70afd0d4ec8821105e506d7a20f9af01b8eafb (diff) | |
| download | gem5-52c8ae5187cb6ba8d15a8de6526f56defe541f5b.tar.xz | |
mem: Enforce insertion order on the cache response path
This patch enforces insertion order transmission of packets on the
response path in the cache. Note that the logic to enforce order is
already present in the packet queue, this patch simply turns it on for
queues in the response path.
Without this patch, there are corner cases where a request-response is
faster than a response-response forwarded through the cache. This
violation of queuing order causes problems in the snoop filter leaving
it with inaccurate information. This causes assert failures in the
snoop filter later on.
A follow on patch relaxes the order enforcement in the packet queue to
limit the performance impact.
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/cache.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc index aa95d5604..a03790abc 100644 --- a/src/mem/cache/cache.cc +++ b/src/mem/cache/cache.cc @@ -666,7 +666,7 @@ Cache::recvTimingReq(PacketPtr pkt) // lat, neglecting responseLatency, modelling hit latency // just as lookupLatency or or the value of lat overriden // by access(), that calls accessBlock() function. - cpuSidePort->schedTimingResp(pkt, request_time); + cpuSidePort->schedTimingResp(pkt, request_time, true); } else { // queue the packet for deletion, as the sending cache is // still relying on it; if the block is found in access(), @@ -723,7 +723,7 @@ Cache::recvTimingReq(PacketPtr pkt) std::memset(pkt->getPtr<uint8_t>(), 0xFF, pkt->getSize()); // request_time is used here, taking into account lat and the delay // charged if the packet comes from the xbar. - cpuSidePort->schedTimingResp(pkt, request_time); + cpuSidePort->schedTimingResp(pkt, request_time, true); // If an outstanding request is in progress (we found an // MSHR) this is set to null @@ -1330,7 +1330,7 @@ Cache::recvTimingResp(PacketPtr pkt) } // Reset the bus additional time as it is now accounted for tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; - cpuSidePort->schedTimingResp(tgt_pkt, completion_time); + cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); break; case MSHR::Target::FromPrefetcher: |