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authorSteve Reinhardt <stever@eecs.umich.edu>2006-10-21 23:35:00 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2006-10-21 23:35:00 -0700
commit5e2263fc523633af81a81ed7cea2cf72bd57efbb (patch)
treeff0568a58123097440f67f6f966aae0004ee3053 /src/mem/cache
parent0159529343f31cc4a4496d5b5c2939f8e2e0bb95 (diff)
downloadgem5-5e2263fc523633af81a81ed7cea2cf72bd57efbb.tar.xz
Small bug fixes for timing LL/SC. Better now but
not necessarily 100% there yet. src/mem/cache/cache_impl.hh: Generate response packet on failed store conditional. src/mem/packet.hh: Clear packet flags when reinitializing. (SATISFIED in particular is one we don't want to leave set.) --HG-- extra : convert_revision : 29207c8a09afcbce43f41c480ad0c1b21d47454f
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/cache_impl.hh7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 64f658907..3c47762f6 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -232,7 +232,12 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
}
}
- if (!(pkt->flags & SATISFIED)) {
+ if (pkt->flags & SATISFIED) {
+ // happens when a store conditional fails because it missed
+ // the cache completely
+ if (pkt->needsResponse())
+ respond(pkt, curTick+lat);
+ } else {
missQueue->handleMiss(pkt, size, curTick + hitLatency);
}