diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-02-19 05:56:06 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-02-19 05:56:06 -0500 |
| commit | 7cd49b24d2523eaf21179946e291c46c6acf5bfc (patch) | |
| tree | 91c066608dfb6e4ca52dd25e91a61719848d64a7 /src/mem/cache | |
| parent | 5c7ebee434a0328802c01b38c19845c50ae75cab (diff) | |
| download | gem5-7cd49b24d2523eaf21179946e291c46c6acf5bfc.tar.xz | |
sim: Make clock private and access using clockPeriod()
This patch makes the clock member private to the ClockedObject and
forces all children to access it using clockPeriod(). This makes it
impossible to inadvertently change the clock, and also makes it easier
to transition to a situation where the clock is derived from e.g. a
clock domain, or through a multiplier.
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 10 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/base.cc | 2 |
2 files changed, 7 insertions, 5 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index d2c9f900e..a7e6a6186 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012 ARM Limited + * Copyright (c) 2010-2013 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -898,7 +898,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt) // responseLatency is the latency of the return path // from lower level caches/memory to an upper level cache or // the core. - completion_time = responseLatency * clock + + completion_time = responseLatency * clockPeriod() + (transfer_offset ? pkt->finishTime : pkt->firstWordTime); assert(!target->pkt->req->isUncacheable()); @@ -914,13 +914,15 @@ Cache<TagStore>::handleResponse(PacketPtr pkt) // responseLatency is the latency of the return path // from lower level caches/memory to an upper level cache or // the core. - completion_time = responseLatency * clock + pkt->finishTime; + completion_time = responseLatency * clockPeriod() + + pkt->finishTime; target->pkt->req->setExtraData(0); } else { // not a cache fill, just forwarding response // responseLatency is the latency of the return path // from lower level cahces/memory to the core. - completion_time = responseLatency * clock + pkt->finishTime; + completion_time = responseLatency * clockPeriod() + + pkt->finishTime; if (pkt->isRead() && !is_error) { target->pkt->setData(pkt->getPtr<uint8_t>()); } diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc index be05a464f..ddf1c1b31 100644 --- a/src/mem/cache/prefetch/base.cc +++ b/src/mem/cache/prefetch/base.cc @@ -241,7 +241,7 @@ BasePrefetcher::notify(PacketPtr &pkt, Tick time) prefetch->req->setThreadContext(pkt->req->contextId(), pkt->req->threadId()); - prefetch->time = time + clock * *delayIter; + prefetch->time = time + clockPeriod() * *delayIter; // We just remove the head if we are full if (pf.size() == size) { |