rename store conditional stuff as extra data so it can be used for conditional swaps as well

Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic

src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
    add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
    Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
    Make atomic memory ops atomic
    Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
    add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
    remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
    swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
    add a post access code block
src/arch/sparc/isa/includes.isa:
    need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
    add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
    add support for twinloads
    add support for swap and conditional swap instructions
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
    Add support for atomic swap memory commands
src/mem/packet_access.hh:
    Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
    Add support for atomic swap memory commands
    Rename sc code to extradata

--HG--
extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656

2 files changed, 3 insertions, 3 deletions

diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index 7b999e4b1..a4df1b03f 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -249,7 +249,7 @@ class CacheBlk
                 }
             }
 
-            req->setScResult(success ? 1 : 0);
+            req->setExtraData(success ? 1 : 0);
             clearLoadLocks();
             return success;
         } else {
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index ff35a0749..dac2b93a4 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -206,7 +206,7 @@ Cache<TagStore,Coherence>::handleAccess(PacketPtr &pkt, int & lat,
         // complete miss (no matching block)
         if (pkt->req->isLocked() && pkt->isWrite()) {
             // miss on store conditional... just give up now
-            pkt->req->setScResult(0);
+            pkt->req->setExtraData(0);
             pkt->flags |= SATISFIED;
         }
     }
@@ -1147,7 +1147,7 @@ Cache<TagStore,Coherence>::CpuSidePort::recvTiming(PacketPtr pkt)
     }
 
     if (pkt->isWrite() && (pkt->req->isLocked())) {
-        pkt->req->setScResult(1);
+        pkt->req->setExtraData(1);
     }
     myCache()->access(pkt);
     return true;