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authorRon Dreslinski <rdreslin@umich.edu>2006-11-12 06:35:39 -0500
committerRon Dreslinski <rdreslin@umich.edu>2006-11-12 06:35:39 -0500
commitc577665040342bf27808bfdea272626e4dac786d (patch)
treea635e61b9b235130f613150706812790258b8414 /src/mem/cache
parentf876bc2bf0e04b888c2748c0cabf8d11b31f41b7 (diff)
downloadgem5-c577665040342bf27808bfdea272626e4dac786d.tar.xz
Fix functional access errors related to delayed respnoses in cachePort
src/mem/cache/base_cache.cc: On a delayed response, be sure to call the fixPacket wrapper to toggle hasData flag. src/mem/packet.cc: src/mem/packet.hh: Create a wrapper to toggle the hasData flag on delayed responses --HG-- extra : convert_revision : 1ced8d4e3dc12a059fb7636d59e429cd3dd46901
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/base_cache.cc11
1 files changed, 8 insertions, 3 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 489a24d4c..c16cb6945 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -114,6 +114,8 @@ BaseCache::CachePort::checkFunctional(PacketPtr pkt)
// If the target contains data, and it overlaps the
// probed request, need to update data
if (target->intersect(pkt)) {
+ DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a drain\n",
+ pkt->cmdString(), pkt->getAddr() & ~(cache->getBlockSize() - 1));
notDone = fixPacket(pkt, target);
}
i++;
@@ -126,8 +128,11 @@ BaseCache::CachePort::checkFunctional(PacketPtr pkt)
PacketPtr target = j->second;
// If the target contains data, and it overlaps the
// probed request, need to update data
- if (target->intersect(pkt))
- notDone = fixPacket(pkt, target);
+ if (target->intersect(pkt)) {
+ DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a response\n",
+ pkt->cmdString(), pkt->getAddr() & ~(cache->getBlockSize() - 1));
+ notDone = fixDelayedResponsePacket(pkt, target);
+ }
j++;
}
return notDone;
@@ -348,7 +353,7 @@ BaseCache::CacheEvent::process()
}
return;
}
- //Else it's a response Response
+ //Else it's a response
assert(cachePort->transmitList.size());
assert(cachePort->transmitList.front().first <= curTick);
pkt = cachePort->transmitList.front().second;