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authorRon Dreslinski <rdreslin@umich.edu>2006-10-12 14:21:25 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-12 14:21:25 -0400
commitfe230ddb8ff2f3339ffaa20d30c01bb5b00185b6 (patch)
tree53bdcaa40d559a0a7eabad0656a2b257f34f963e /src/mem/cache
parentf89b56b61ad9cb4605d0c3297b5d563672812ce9 (diff)
downloadgem5-fe230ddb8ff2f3339ffaa20d30c01bb5b00185b6.tar.xz
Remove bus and top level parameters from cache
src/mem/cache/base_cache.hh: Remove top level param from cache src/mem/cache/coherence/uni_coherence.cc: Remove top level parameters from the cache --HG-- extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/base_cache.hh27
-rw-r--r--src/mem/cache/cache_impl.hh9
-rw-r--r--src/mem/cache/coherence/uni_coherence.cc14
3 files changed, 10 insertions, 40 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 563b1ca8b..455e13d9c 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -212,10 +212,6 @@ class BaseCache : public MemObject
protected:
- /** True if this cache is connected to the CPU. */
- bool topLevelCache;
-
-
/** Stores time the cache blocked for statistics. */
Tick blockedCycle;
@@ -337,7 +333,7 @@ class BaseCache : public MemObject
*/
BaseCache(const std::string &name, Params &params)
: MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
- slaveRequests(0), topLevelCache(false), blkSize(params.blkSize),
+ slaveRequests(0), blkSize(params.blkSize),
missCount(params.maxMisses)
{
//Start ports at null if more than one is created we should panic
@@ -358,15 +354,6 @@ class BaseCache : public MemObject
}
/**
- * Returns true if this cache is connect to the CPU.
- * @return True if this is a L1 cache.
- */
- bool isTopLevel()
- {
- return topLevelCache;
- }
-
- /**
* Returns true if the cache is blocked for accesses.
*/
bool isBlocked()
@@ -561,8 +548,6 @@ class BaseCache : public MemObject
*/
void respondToSnoop(Packet *pkt, Tick time)
{
-// assert("Implement\n" && 0);
-// mi->respond(pkt,curTick + hitLatency);
assert (pkt->needsResponse());
CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
reqMem->schedule(time);
@@ -585,15 +570,7 @@ class BaseCache : public MemObject
{
//This is where snoops get updated
AddrRangeList dummy;
-// if (!topLevelCache)
-// {
- cpuSidePort->getPeerAddressRanges(dummy, snoop);
-// }
-// else
-// {
-// snoop.push_back(RangeSize(0,-1));
-// }
-
+ cpuSidePort->getPeerAddressRanges(dummy, snoop);
return;
}
}
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 150abbe52..9db79b843 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -151,12 +151,7 @@ Cache(const std::string &_name,
doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
hitLatency(params.hitLatency)
{
-//FIX BUS POINTERS
-// if (params.in == NULL) {
- topLevelCache = true;
-// }
-//PLEASE FIX THIS, BUS SIZES NOT BEING USED
- tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
+ tags->setCache(this);
tags->setPrefetcher(prefetcher);
missQueue->setCache(this);
missQueue->setPrefetcher(prefetcher);
@@ -397,7 +392,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
BlkType *blk = tags->findBlock(pkt);
MSHR *mshr = missQueue->findMSHR(blk_addr);
- if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
+ if (coherence->hasProtocol()) { //@todo Move this into handle bus req
//If we find an mshr, and it is in service, we need to NACK or invalidate
if (mshr) {
if (mshr->inService) {
diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc
index 5ab706269..0efe393f9 100644
--- a/src/mem/cache/coherence/uni_coherence.cc
+++ b/src/mem/cache/coherence/uni_coherence.cc
@@ -68,14 +68,12 @@ UniCoherence::handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
if (pkt->isInvalidate()) {
DPRINTF(Cache, "snoop inval on blk %x (blk ptr %x)\n",
pkt->getAddr(), blk);
- if (!cache->isTopLevel()) {
- // Forward to other caches
- Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
- cshrs.allocate(tmp);
- cache->setSlaveRequest(Request_Coherence, curTick);
- if (cshrs.isFull()) {
- cache->setBlockedForSnoop(Blocked_Coherence);
- }
+ // Forward to other caches
+ Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
+ cshrs.allocate(tmp);
+ cache->setSlaveRequest(Request_Coherence, curTick);
+ if (cshrs.isFull()) {
+ cache->setBlockedForSnoop(Blocked_Coherence);
}
} else {
if (blk) {