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authorAndreas Hansson <andreas.hansson@arm.com>2013-02-19 05:56:06 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2013-02-19 05:56:06 -0500
commit860155a5fc48f983e9af40c19bf8db8250709c26 (patch)
tree18c5c3ccb573182ba8444fae02c2c84f2bb4a3c5 /src/mem/cache
parent40d0e6c899d5da400c9647496532a8fb1ef64b7b (diff)
downloadgem5-860155a5fc48f983e9af40c19bf8db8250709c26.tar.xz
mem: Enforce strict use of busFirst- and busLastWordTime
This patch adds a check to ensure that the delay incurred by the bus is not simply disregarded, but accounted for by someone. At this point, all the modules do is to zero it out, and no additional time is spent. This highlights where the bus timing is simply dropped instead of being paid for. As a follow up, the locations identified in this patch should add this additional time to the packets in one way or another. For now it simply acts as a sanity check and highlights where the delay is simply ignored. Since no time is added, all regressions remain the same.
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/cache_impl.hh20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 8fd28728b..b30132748 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -381,6 +381,8 @@ Cache<TagStore>::recvTimingSnoopResp(PacketPtr pkt)
pkt->setDest(rec->prevSrc);
delete rec;
+ // @todo someone should pay for this
+ pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
memSidePort->schedTimingSnoopResp(pkt, time);
}
@@ -419,6 +421,9 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
// supplier had exclusive copy to begin with.
if (pkt->needsExclusive() && !pkt->isSupplyExclusive()) {
Packet *snoopPkt = new Packet(pkt, true); // clear flags
+ // also reset the bus time that the original packet has
+ // not yet paid for
+ snoopPkt->busFirstWordDelay = snoopPkt->busLastWordDelay = 0;
snoopPkt->setExpressSnoop();
snoopPkt->assertMemInhibit();
memSidePort->sendTimingReq(snoopPkt);
@@ -437,6 +442,9 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
if (pkt->req->isUncacheable()) {
uncacheableFlush(pkt);
+ // @todo: someone should pay for this
+ pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
+
// writes go in write buffer, reads use MSHR
if (pkt->isWrite() && !pkt->isRead()) {
allocateWriteBuffer(pkt, time, true);
@@ -489,6 +497,8 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
if (needsResponse) {
pkt->makeTimingResponse();
+ // @todo: Make someone pay for this
+ pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
cpuSidePort->schedTimingResp(pkt, clockEdge(lat));
} else {
/// @todo nominally we should just delete the packet here,
@@ -499,6 +509,9 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
} else {
// miss
+ // @todo: Make someone pay for this
+ pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
+
Addr blk_addr = blockAlign(pkt->getAddr());
MSHR *mshr = mshrQueue.findMatch(blk_addr);
@@ -946,6 +959,8 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
// isInvalidate() set otherwise.
target->pkt->cmd = MemCmd::ReadRespWithInvalidate;
}
+ // reset the bus additional time as it is now accounted for
+ target->pkt->busFirstWordDelay = target->pkt->busLastWordDelay = 0;
cpuSidePort->schedTimingResp(target->pkt, completion_time);
break;
@@ -1250,6 +1265,8 @@ doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
assert(req_pkt->isInvalidate() || pkt->sharedAsserted());
pkt->allocate();
pkt->makeTimingResponse();
+ // @todo Make someone pay for this
+ pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
if (pkt->isRead()) {
pkt->setDataFromBlock(blk_data, blkSize);
}
@@ -1293,6 +1310,9 @@ Cache<TagStore>::handleSnoop(PacketPtr pkt, BlkType *blk,
Packet snoopPkt(pkt, true); // clear flags
snoopPkt.setExpressSnoop();
snoopPkt.pushSenderState(new ForwardResponseRecord(pkt->getSrc()));
+ // the snoop packet does not need to wait any additional
+ // time
+ snoopPkt.busFirstWordDelay = snoopPkt.busLastWordDelay = 0;
cpuSidePort->sendTimingSnoopReq(&snoopPkt);
if (snoopPkt.memInhibitAsserted()) {
// cache-to-cache response from some upper cache