summaryrefslogtreecommitdiff
path: root/src/mem/cache
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2012-08-22 11:39:59 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-08-22 11:39:59 -0400
commitc60db56741631b03e3431d03c26c9114c27ba6c6 (patch)
tree646cb63e6a355ca2e61569c7e8ce150b7776f12e /src/mem/cache
parenta6074016e211276e47238d0d708288527ace0aef (diff)
downloadgem5-c60db56741631b03e3431d03c26c9114c27ba6c6.tar.xz
Packet: Remove NACKs from packet and its use in endpoints
This patch removes the NACK frrom the packet as there is no longer any module in the system that issues them (the bridge was the only one and the previous patch removes that). The handling of NACKs was mostly avoided throughout the code base, by using e.g. panic or assert false, but in a few locations the NACKs were actually dealt with (although NACKs never occured in any of the regressions). Most notably, the DMA port will now never receive a NACK and the backoff time is thus never changed. As a consequence, the entire backoff mechanism (similar to a PCI bus) is now removed and the DMA port entirely relies on the bus performing the arbitration and issuing a retry when appropriate. This is more in line with e.g. PCIe. Surprisingly, this patch has no impact on any of the regressions. As mentioned in the patch that removes the NACK from the bridge, a follow-up patch should change the request and response buffer size for at least one regression to also verify that the system behaves as expected when the bridge fills up.
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/cache_impl.hh14
1 files changed, 0 insertions, 14 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 4d8adbd90..2fdbc5c1d 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -692,8 +692,6 @@ Cache<TagStore>::atomicAccess(PacketPtr pkt)
DPRINTF(Cache, "Receive response: %s for addr %x in state %i\n",
bus_pkt->cmdString(), bus_pkt->getAddr(), old_state);
- assert(!bus_pkt->wasNacked());
-
// If packet was a forward, the response (if any) is already
// in place in the bus_pkt == pkt structure, so we don't need
// to do anything. Otherwise, use the separate bus_pkt to
@@ -823,12 +821,6 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
assert(mshr);
- if (pkt->wasNacked()) {
- //pkt->reinitFromRequest();
- warn("NACKs from devices not connected to the same bus "
- "not implemented\n");
- return;
- }
if (is_error) {
DPRINTF(Cache, "Cache received packet with error for address %x, "
"cmd: %s\n", pkt->getAddr(), pkt->cmdString());
@@ -1644,12 +1636,6 @@ template<class TagStore>
bool
Cache<TagStore>::MemSidePort::recvTimingResp(PacketPtr pkt)
{
- // this needs to be fixed so that the cache updates the mshr and sends the
- // packet back out on the link, but it probably won't happen so until this
- // gets fixed, just panic when it does
- if (pkt->wasNacked())
- panic("Need to implement cache resending nacked packets!\n");
-
cache->handleResponse(pkt);
return true;
}