summaryrefslogtreecommitdiff
path: root/src/mem/cache
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2012-01-17 12:55:09 -0600
committerAndreas Hansson <andreas.hansson@arm.com>2012-01-17 12:55:09 -0600
commitde34e49d15b95cc8be51dbed2e98c469e7486959 (patch)
treefc3d2ab7d4c8c75fedbff44bb29d479c620eb620 /src/mem/cache
parentb3f930c884ef23e4d784553fdccc91a772334fd7 (diff)
downloadgem5-de34e49d15b95cc8be51dbed2e98c469e7486959.tar.xz
MEM: Simplify ports by removing EventManager
This patch removes the inheritance of EventManager from the ports and moves all responsibility for event queues to the owner. Eventually the event manager should be the interface block, which could either be the structural owner or a subblock like a LSQ in the O3 CPU for example.
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/base.cc2
-rw-r--r--src/mem/cache/cache_impl.hh2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 7863edde0..023b74323 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -126,7 +126,7 @@ BaseCache::CachePort::clearBlocked()
mustSendRetry = false;
SendRetryEvent *ev = new SendRetryEvent(this, true);
// @TODO: need to find a better time (next bus cycle?)
- schedule(ev, curTick() + 1);
+ cache->schedule(ev, curTick() + 1);
}
}
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 453e62b1a..581435010 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1729,7 +1729,7 @@ Cache<TagStore>::MemSidePort::sendPacket()
// @TODO: need to facotr in prefetch requests here somehow
if (nextReady != MaxTick) {
DPRINTF(CachePort, "more packets to send @ %d\n", nextReady);
- schedule(sendEvent, std::max(nextReady, curTick() + 1));
+ cache->schedule(sendEvent, std::max(nextReady, curTick() + 1));
} else {
// no more to send right now: if we're draining, we may be done
if (drainEvent && !sendEvent->scheduled()) {