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authorAndreas Hansson <andreas.hansson@arm.com>2013-06-27 05:49:49 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-06-27 05:49:49 -0400
commit33a8d777add840cae1938a1fbe9e155840769a38 (patch)
treec0f4a0bb6f04a2b07b013b0ed96522eeb38311c2 /src/mem/cache
parent10650fc5257c2351e95292747ad6099cea9dfb1f (diff)
downloadgem5-33a8d777add840cae1938a1fbe9e155840769a38.tar.xz
mem: Align cache timing to clock edges
This patch changes the cache timing calculations such that the results are aligned to clock edges. Plenty stats change as a results of this patch.
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/cache_impl.hh10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index f697f84e4..7098dbfd3 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -929,7 +929,7 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
// responseLatency is the latency of the return path
// from lower level caches/memory to an upper level cache or
// the core.
- completion_time = curTick() + responseLatency * clockPeriod() +
+ completion_time = clockEdge(responseLatency) +
(transfer_offset ? pkt->busLastWordDelay :
pkt->busFirstWordDelay);
@@ -946,14 +946,14 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
// responseLatency is the latency of the return path
// from lower level caches/memory to an upper level cache or
// the core.
- completion_time = curTick() + responseLatency * clockPeriod() +
+ completion_time = clockEdge(responseLatency) +
pkt->busLastWordDelay;
target->pkt->req->setExtraData(0);
} else {
// not a cache fill, just forwarding response
// responseLatency is the latency of the return path
// from lower level cahces/memory to the core.
- completion_time = curTick() + responseLatency * clockPeriod() +
+ completion_time = clockEdge(responseLatency) +
pkt->busLastWordDelay;
if (pkt->isRead() && !is_error) {
target->pkt->setData(pkt->getPtr<uint8_t>());
@@ -1021,7 +1021,7 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
}
mq = mshr->queue;
mq->markPending(mshr);
- requestMemSideBus((RequestCause)mq->index, curTick() +
+ requestMemSideBus((RequestCause)mq->index, clockEdge() +
pkt->busLastWordDelay);
} else {
mq->deallocate(mshr);
@@ -1257,7 +1257,7 @@ Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk,
std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
}
- blk->whenReady = curTick() + responseLatency * clockPeriod() +
+ blk->whenReady = clockEdge() + responseLatency * clockPeriod() +
pkt->busLastWordDelay;
return blk;