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authorAndreas Hansson <andreas.hansson@arm.com>2014-09-19 10:35:04 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-09-19 10:35:04 -0400
commit38646d48ebd32c551ce3c478e9dee47f83acdf1e (patch)
tree246553b3843f866a62eff0644339372a0e885575 /src/mem/cache
parent2ccdfc547d5b58bdc859e4497658e972d7af5c45 (diff)
downloadgem5-38646d48ebd32c551ce3c478e9dee47f83acdf1e.tar.xz
mem: Add checks to sendTimingReq in cache
A small fix to ensure the return value is not ignored.
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/cache_impl.hh9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a792de19d..8c091fa39 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -462,7 +462,9 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
// Just forward the packet if caches are disabled.
if (system->bypassCaches()) {
- memSidePort->sendTimingReq(pkt);
+ // @todo This should really enqueue the packet rather
+ bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
+ assert(success);
return true;
}
@@ -483,7 +485,10 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
snoopPkt->busFirstWordDelay = snoopPkt->busLastWordDelay = 0;
snoopPkt->setExpressSnoop();
snoopPkt->assertMemInhibit();
- memSidePort->sendTimingReq(snoopPkt);
+ bool M5_VAR_USED success = memSidePort->sendTimingReq(snoopPkt);
+ // the packet is marked inhibited and will thus bypass any
+ // flow control
+ assert(success);
// main memory will delete snoopPkt
}
// since we're the official target but we aren't responding,